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Steven J. E. Wilton: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zion Kwok, Steven J. E. Wilton
    Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:35-44 [Conf]
  2. Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, S. Lopez-Buedo
    Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:35-44 [Conf]
  3. Peter Hallschmid, Steven J. E. Wilton
    Detailed routing architectures for embedded programmable logic IP cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:69-74 [Conf]
  4. Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton
    Architectures and algorithms for synthesizable embedded programmable logic cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:3-11 [Conf]
  5. Julien Lamoureux, Steven J. E. Wilton
    FPGA clock network architecture: flexibility vs. area and power. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:101-108 [Conf]
  6. Andy Yan, Rebecca Cheng, Steven J. E. Wilton
    On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:147-156 [Conf]
  7. Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
    GlitchLess: an active glitch minimization technique for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:156-165 [Conf]
  8. Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
    A synthesizable datapath-oriented embedded FPGA fabric. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:33-41 [Conf]
  9. Steven J. E. Wilton
    Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:67-74 [Conf]
  10. Steven J. E. Wilton
    A crosstalk-aware timing-driven router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:21-28 [Conf]
  11. Steven J. E. Wilton
    SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:171-178 [Conf]
  12. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Architecture of Centralized Field-Configurable Memory. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:97-103 [Conf]
  13. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:10-16 [Conf]
  14. William K. C. Ho, Steven J. E. Wilton
    Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:111-123 [Conf]
  15. Winnie W. Cheng, Steven J. E. Wilton, Babak Hamidzadeh
    FPGA Implementation of a Prototype WDM On-Line Scheduler. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:773-776 [Conf]
  16. Ernie Lin, Steven J. E. Wilton
    Macrocell Architectures for Product Term Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:48-58 [Conf]
  17. M. Imran Masud, Steven J. E. Wilton
    A New Switch Block for Segmented FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:274-281 [Conf]
  18. Kara K. W. Poon, Andy Yan, Steven J. E. Wilton
    A Flexible Power Model for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:312-321 [Conf]
  19. Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
    The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:719-728 [Conf]
  20. C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
    Dynamic Voltage Scaling for Commercial FPGAs. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:173-180 [Conf]
  21. Bradley R. Quinton, Steven J. E. Wilton
    Post-Silicon Debug Using Programmable Logic Cores. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:241-248 [Conf]
  22. Julien Lamoureux, Steven J. E. Wilton
    On the Interaction Between Power-Aware FPGA CAD Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:701-708 [Conf]
  23. Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
    Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:267-274 [Conf]
  24. Norman P. Jouppi, Steven J. E. Wilton
    Tradeoffs in Two-Level On-Chip Caching. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:34-45 [Conf]
  25. Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
    A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1945-1948 [Conf]
  26. Bradley R. Quinton, Steven J. E. Wilton
    Concentrator access networks for programmable logic cores on SoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:45-48 [Conf]
  27. Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux
    An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:885-888 [Conf]
  28. Lei He, Mike Hutton, Tim Tuan, Steve Wilton
    Challenges and opportunities for low power FPGAs in nanometer technologies. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:90- [Conf]
  29. Steven J. E. Wilton, Zvonko G. Vranesic
    Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:51-55 [Conf]
  30. Steven J. E. Wilton
    Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:56-68 [Journal]
  31. Kara K. W. Poon, Steven J. E. Wilton, Andy Yan
    A detailed power model for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:2, pp:279-302 [Journal]
  32. Peter Hallschmid, Steven J. E. Wilton
    Routing architecture optimizations for high-density embedded programmable IP cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1320-1324 [Journal]
  33. Andy Yan, Steven J. E. Wilton
    Product-Term-Based Synthesizable Embedded Programmable Logic Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:474-488 [Journal]
  34. Julien Lamoureux, Steven J. E. Wilton
    Architecture and CAD for FPGA Clock Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  35. Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton
    Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  36. Julien Lamoureux, Steven J. E. Wilton
    Activity Estimation for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  37. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    The memory/logic interface in FPGAs with large embedded memory arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:80-91 [Journal]
  38. Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
    Structural analysis and generation of synthetic digital circuits with memory. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:223-226 [Journal]
  39. Julien Lamoureux, Steven J. E. Wilton
    On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:119-132 [Journal]

  40. BackSpace: Formal Analysis for Post-Silicon Debug. [Citation Graph (, )][DBLP]


  41. Wirelength modeling for homogeneous and heterogeneous FPGA architectural development. [Citation Graph (, )][DBLP]


  42. The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). [Citation Graph (, )][DBLP]


  43. Clock-Aware Placement for FPGAs. [Citation Graph (, )][DBLP]


  44. Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. [Citation Graph (, )][DBLP]


  45. Embedded Programmable Logic Core Enhancements for System Bus Interfaces. [Citation Graph (, )][DBLP]


  46. Rapid estimation of power consumption for hybrid FPGAs. [Citation Graph (, )][DBLP]


  47. An analytical model describing the relationships between logic architecture and FPGA density. [Citation Graph (, )][DBLP]


  48. Improving the memory footprint and runtime scalability of FPGA CAD algorithms. [Citation Graph (, )][DBLP]


  49. An analytical model relating FPGA architecture and place and route runtime. [Citation Graph (, )][DBLP]


  50. Modeling post-techmapping and post-clustering FPGA circuit depth. [Citation Graph (, )][DBLP]


  51. Accelerating trace computation in post-silicon debug. [Citation Graph (, )][DBLP]


  52. Towards Analytical Methods for FPGA Architecture Investigation. [Citation Graph (, )][DBLP]


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