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John McAllister: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jasmine Lam, John McAllister, Jennifer Dudley
    Core-Based Methodology: An Automated Approach for Implementing a Complete System from Algorithms to a Heterogeneous Network including FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:325-326 [Conf]
  2. S. Fischaber, R. Hasson, John McAllister, Roger Woods
    FPGA Core Network Implementation and Optimization: A Case Study. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:319-320 [Conf]
  3. John McAllister, Roger Woods, D. Reilly, S. Fischaber, R. Hasson
    Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:414-423 [Conf]
  4. John McAllister, Roger Woods, Richard Walke
    Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:254-263 [Conf]
  5. John McAllister, Roger Woods, S. Fischaber, E. Malins
    Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:511-523 [Journal]
  6. John McAllister, Roger Woods, Richard Walke, D. Reilly
    Multidimensional DSP Core Synthesis for FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:207-221 [Journal]

  7. Muir Hardware Synthesis for Multimedia Applications. [Citation Graph (, )][DBLP]


  8. Power efficient DSP datapath configuration methodology for FPGA. [Citation Graph (, )][DBLP]


  9. Introduction to System Level Design for Heterogeneous Systems. [Citation Graph (, )][DBLP]


  10. Memory-Centric Hardware Synthesis from Dataflow Models. [Citation Graph (, )][DBLP]


  11. SOC Memory Hierarchy Derivation from Dataflow Graphs. [Citation Graph (, )][DBLP]


  12. Reduced-complexity MSGR-based matrix inversion. [Citation Graph (, )][DBLP]


  13. Power efficient dynamic-range utilisation for DSP on FPGA. [Citation Graph (, )][DBLP]


  14. Modified givens rotations and their application to matrix inversion. [Citation Graph (, )][DBLP]


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