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Lesley Shannon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lesley Shannon, Paul Chow
    Standardizing the Performance Assessment of Reconfigurable Processor Architectures. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:282-283 [Conf]
  2. Lesley Shannon, Paul Chow
    Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. [Citation Graph (0, 0)][DBLP]
    FCCM, 2005, pp:63-72 [Conf]
  3. Manuel Saldaña, Lesley Shannon, Paul Chow
    The routability of multiprocessor network topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:232- [Conf]
  4. Lesley Shannon, Paul Chow
    Using reconfigurability to achieve real-time profiling for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:190-199 [Conf]
  5. Lesley Shannon, Paul Chow
    Leveraging Reconfigurability in the Design Process. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:731-732 [Conf]
  6. Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
    Designing an FPGA SoC Using a Standardized IP Block Interface. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:341-342 [Conf]
  7. Manuel Saldaña, Lesley Shannon, Paul Chow
    The routability of multiprocessor network topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:49-56 [Conf]
  8. Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
    A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  9. Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow
    Routability of Network Topologies in FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:948-951 [Journal]
  10. Lesley Shannon, Paul Chow
    SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:4, pp:377-390 [Journal]

  11. Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms. [Citation Graph (, )][DBLP]


  12. A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator. [Citation Graph (, )][DBLP]


  13. Facilitating Processor-Based DPR Systems for non-DPR Experts. [Citation Graph (, )][DBLP]


  14. Predicting the performance of application-specific NoCs implemented on FPGAs. [Citation Graph (, )][DBLP]


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