The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

K. N. Vikram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. K. N. Vikram, V. Vasudevan
    Scheduling divisible loads on partially reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:289-290 [Conf]
  2. K. N. Vikram, V. Vasudevan
    Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:1010-1023 [Journal]
  3. K. N. Vikram, V. Vasudevan
    Hardware-software co-simulation of bus-based reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:4, pp:133-144 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002