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Publications of Author

1. Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
   Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:299-300 [Conf]
   
2. Roy Mader, Ivan S. Kourtev
   Reduced dynamic swing domino logic. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2003, pp:33-36 [Conf]
   
3. Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
   Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:314-317 [Conf]
   
4. Ivan S. Kourtev, Eby G. Friedman
   Clock skew scheduling for improved reliability via quadratic programming. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1999, pp:239-243 [Conf]
   
5. Rajani Parthasarthy, Ivan S. Kourtev
   Performance metrics for asynchronous digital circuits applicable to computer-aided design. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:301-304 [Conf]
   
6. Baris Taskin, Ivan S. Kourtev
   Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2004, pp:617-620 [Conf]
   
7. Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev
   Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2002, pp:357-360 [Conf]
   
8. Baris Taskin, Ivan S. Kourtev
   Delay insertion method in clock skew scheduling. [Citation Graph (0, 0)][DBLP]
   ISPD, 2005, pp:47-54 [Conf]
   
9. Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis
   Short Courses in System-on-a-Chip (SoC) Design. [Citation Graph (0, 0)][DBLP]
   MSE, 2003, pp:126-127 [Conf]
   
10. Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis
    The Sandbox Design Experience Course. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:39-40 [Conf]
    
11. Baris Taskin, Ivan S. Kourtev
    Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:111-118 [Conf]
    
12. Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman
    Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:231-246 [Journal]
    
13. Baris Taskin, Ivan S. Kourtev
    Delay Insertion Method in Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:651-663 [Journal]
    
14. Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
    Substrate coupling in digital circuits in mixed-signal smart-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:67-78 [Journal]
    
15. Baris Taskin, Ivan S. Kourtev
    Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:12-27 [Journal]
    
16. Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones
    Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:7, pp:445-456 [Journal]