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Publications of Author

1. Uday Bondhugula, Ananth Devulapalli, James Dinan, Joseph Fernando, Pete Wyckoff, Eric Stahlberg, P. Sadayappan
   Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths. [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:152-164 [Conf]
   
2. Sayantan Sur, U. K. R. Bondhugula, Amith R. Mamidala, Hyun-Wook Jin, Dhabaleswar K. Panda
   High Performance RDMA Based All-to-All Broadcast for InfiniBand Clusters. [Citation Graph (0, 0)][DBLP]
   HiPC, 2005, pp:148-157 [Conf]
   
3. Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, P. Sadayappan
   Parallel FPGA-based all-pairs shortest-paths in a directed graph. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
4. Uday Bondhugula, J. Ramanujam, P. Sadayappan
   Automatic mapping of nested loops to FPGAS. [Citation Graph (0, 0)][DBLP]
   PPOPP, 2007, pp:101-111 [Conf]
   
5. Sriram Krishnamoorthy, Muthu Baskaran, Uday Bondhugula, J. Ramanujam, Atanas Rountev, P. Sadayappan
   Effective automatic parallelization of stencil computations. [Citation Graph (0, 0)][DBLP]
   PLDI, 2007, pp:235-244 [Conf]
   
6. 
   Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors. [Citation Graph (, )][DBLP]
   
   
7. 
   Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model. [Citation Graph (, )][DBLP]
   
   
8. 
   A compiler framework for optimization of affine loop nests for gpgpus. [Citation Graph (, )][DBLP]
   
   
9. 
   Towards effective automatic parallelization for multicore systems. [Citation Graph (, )][DBLP]
   
   
10. 
    A practical automatic polyhedral parallelizer and locality optimizer. [Citation Graph (, )][DBLP]
    
    
11. 
    Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories. [Citation Graph (, )][DBLP]
    
    
12. 
    Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors. [Citation Graph (, )][DBLP]
    
    
13. 
    Compact multi-dimensional kernel extraction for register tiling. [Citation Graph (, )][DBLP]