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Blair Fort: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Blair Fort, Davor Capalija, Zvonko G. Vranesic, Stephen Dean Brown
    A Multithreaded Soft Processor for SoPC Area Reduction. [Citation Graph (0, 0)][DBLP]
    FCCM, 2006, pp:131-142 [Conf]
  2. Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
    Designing an FPGA SoC Using a Standardized IP Block Interface. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:341-342 [Conf]
  3. Franjo Plavec, Blair Fort, Zvonko G. Vranesic, Stephen Dean Brown
    Experiences with Soft-Core Processor Design. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2005, pp:- [Conf]
  4. Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow
    A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]

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