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Kenji Toda:
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Publications of Author
- Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
Highly Efficient String Matching Circuit for IDS with FPGA. [Citation Graph (0, 0)][DBLP] FCCM, 2006, pp:285-286 [Conf]
- Yoshinori Yamaguchi, Kenji Toda, Jayantha A. Herath, Toshitsugu Yuba
EM-3: A Lisp-Based Data-Driven Machine. [Citation Graph (0, 0)][DBLP] FGCS, 1984, pp:524-532 [Conf]
- Jayantha A. Herath, Nobuo Saito, Kenji Toda, Yoshinori Yamaguchi, Toshitsugu Yuba
DBCL: Data-Flow Computing Base Language with n-Value Logic. [Citation Graph (0, 0)][DBLP] FJCC, 1986, pp:353-361 [Conf]
- Megumi Hisayuki, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda, Kuniyasu Suzaki
Adaptable Load Balancing Using Network Transferable Computer Associated with Mobile IP. [Citation Graph (0, 0)][DBLP] ICDCS Workshops, 2003, pp:8-13 [Conf]
- Megumi Hisayuki, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda, Kuniyasu Suzaki
Dynamic Load Balancing Using Network Transferable Computer. [Citation Graph (0, 0)][DBLP] ICDCS Workshops, 2005, pp:51-57 [Conf]
- Fuminori Nakanishi, Shinnya Hiraike, Shinji Inoue, Yoshiaki Kakuda, Kenji Toda
A Flexible Scheduling for Automobile Control Using Imprecise Computation and Its Fundamental Evaluation. [Citation Graph (0, 0)][DBLP] ICECCS, 2000, pp:210-217 [Conf]
- Naoki Asakawa, Kenji Toda, Yoshimi Takeuchi
Automation of Chamfering by an industrial Robot, for the Case of Machined Hole on a Cylindrical Workpiece. [Citation Graph (0, 0)][DBLP] ICRA, 1998, pp:2452-2457 [Conf]
- Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi
The Execution Model and the Architecture for Real-Time Parallel Systems. [Citation Graph (0, 0)][DBLP] IFIP Congress (1), 1994, pp:177-182 [Conf]
- Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada
Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. [Citation Graph (0, 0)][DBLP] IPPS, 1991, pp:336-343 [Conf]
- Yoshinori Yamaguchi, Kenji Toda, Toshitsugu Yuba
A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3) [Citation Graph (0, 0)][DBLP] ISCA, 1983, pp:363-369 [Conf]
- Kenji Nishida, Kenji Toda, Toshio Shimada, Yoshinori Yamaguchi
The Hardware Architecture of the CODA Real-Time Parallel Processor. [Citation Graph (0, 0)][DBLP] PARCO, 1993, pp:395-402 [Conf]
- Kenji Toda, Yoshinobu Uchibori, Toshitsugu Yuba
The Gene Concept and its Implementation for a Dataflow Schemed Parallel Computer. [Citation Graph (0, 0)][DBLP] PARLE (1), 1989, pp:306-322 [Conf]
- Heejo Lee, Kenji Toda, Jong Kim, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi
Performance comparison of real-time architectures using simulation. [Citation Graph (0, 0)][DBLP] RTCSA, 1995, pp:150-0 [Conf]
- Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi
CODA-R: a reconfigurable testbed for real-time parallel computation. [Citation Graph (0, 0)][DBLP] RTCSA, 1997, pp:252-259 [Conf]
- Hiroyuki Yokoyama, Kenji Toda
FPGA-Based Content Protection System for Embedded Consumer Electronics. [Citation Graph (0, 0)][DBLP] RTCSA, 2005, pp:502-507 [Conf]
- Kenji Toda, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi
A Priority Forwarding Router Chip for Real-Time Interconnection Networks. [Citation Graph (0, 0)][DBLP] IEEE Real-Time Systems Symposium, 1994, pp:63-73 [Conf]
- Toshio Shimada, Kenji Toda, Kenji Nishida
Real-Time Parallel Architecture for Sensor Funsion. [Citation Graph (0, 0)][DBLP] J. Parallel Distrib. Comput., 1992, v:15, n:2, pp:143-152 [Journal]
- Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
Real-world applications of analog and digital evolvable hardware . [Citation Graph (0, 0)][DBLP] IEEE Trans. Evolutionary Computation, 1999, v:3, n:3, pp:220-235 [Journal]
- Yohei Hori, Hiroyuki Yokoyama, Kenji Toda
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration. [Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-4 [Conf]
- Toshihiro Katashita, Atusi Maeda, Kenji Toda, Yoshinori Yamaguchi
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection. [Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-4 [Conf]
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. [Citation Graph (, )][DBLP]
Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]
A priority forwarding scheme for real-time multistage interconnection networks. [Citation Graph (, )][DBLP]
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