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Mark B. Josephs: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Mark B. Josephs, Dennis P. Furey
A Programming Approach to the Design of Asynchronous Logic Blocks. [Citation Graph (0, 0)][DBLP]
Concurrency and Hardware Design, 2002, pp:34-60 [Conf] - Hemangee K. Kapoor, Mark B. Josephs
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. [Citation Graph (0, 0)][DBLP]
ACSD, 2005, pp:58-67 [Conf] - Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. [Citation Graph (0, 0)][DBLP]
ACSD, 2004, pp:89-98 [Conf] - Jun Xu, Reza Sotudeh, Mark B. Josephs
Asynchronous Packet-Switching for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
ACSD, 2006, pp:201-207 [Conf] - Andrew M. Bailey, Mark B. Josephs
Sequencer circuits for VLSI programming. [Citation Graph (0, 0)][DBLP]
ASYNC, 1995, pp:82-90 [Conf] - Mark B. Josephs
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
ASYNC, 2003, pp:121-131 [Conf] - Jelio T. Yantchev, C. G. Huang, Mark B. Josephs, I. M. Nedelchev
Low-latency asynchronous FIFO buffers. [Citation Graph (0, 0)][DBLP]
ASYNC, 1995, pp:24-31 [Conf] - Mark B. Josephs
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR. [Citation Graph (0, 0)][DBLP]
ASYNC, 2007, pp:83-94 [Conf] - Mark B. Josephs
Models for Data-Flow Sequential Processes. [Citation Graph (0, 0)][DBLP]
25 Years Communicating Sequential Processes, 2004, pp:85-97 [Conf] - Mark B. Josephs, Jan Tijmen Udding
An Algebra for Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
CAV, 1990, pp:343-352 [Conf] - Mark B. Josephs, Jan Tijmen Udding
Delay-Insensitive Circuits: An Algebraic Approach to their Design. [Citation Graph (0, 0)][DBLP]
CONCUR, 1990, pp:342-366 [Conf] - Hemangee K. Kapoor, Mark B. Josephs
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. [Citation Graph (0, 0)][DBLP]
DAC, 2004, pp:830-833 [Conf] - Mark B. Josephs, Dennis P. Furey
Delay-Insensitive Interface Specification and Synthesis. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:169-0 [Conf] - Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, Jelio T. Yantchev
High-Level Design of an Asynchronous Packet-Routing Chip. [Citation Graph (0, 0)][DBLP]
Designing Correct Circuits, 1992, pp:261-274 [Conf] - Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding
Normal Form in a Delay-Insensitive Algebra. [Citation Graph (0, 0)][DBLP]
Asynchronous Design Methodologies, 1993, pp:57-70 [Conf] - Mark B. Josephs, Jan Tijmen Udding
Implementing a Stack as a Delay-insensitive Circuit. [Citation Graph (0, 0)][DBLP]
Asynchronous Design Methodologies, 1993, pp:123-135 [Conf] - Mark B. Josephs
Formal Derivation of a Loadable Asynchronous Counter. [Citation Graph (0, 0)][DBLP]
MPC, 1998, pp:234-253 [Conf] - Igor Lemberski, Mark B. Josephs
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions. [Citation Graph (0, 0)][DBLP]
PATMOS, 2002, pp:92-100 [Conf] - Mark B. Josephs
Receptive Process Theory. [Citation Graph (0, 0)][DBLP]
Acta Inf., 1992, v:29, n:1, pp:17-31 [Journal] - Mark B. Josephs
A State-Based Approach to Communicating Processes. [Citation Graph (0, 0)][DBLP]
Distributed Computing, 1988, v:3, n:1, pp:9-18 [Journal] - Iain S. C. Houston, Mark B. Josephs
Specifying Distributed CICS in Z: Accessing Local and Remote Resources (Short Communication). [Citation Graph (0, 0)][DBLP]
Formal Asp. Comput., 1994, v:6, n:5, pp:569-579 [Journal] - Mark B. Josephs, Andrew M. Bailey
The Use of SI-Algebra in the Design of Sequencer Circuits. [Citation Graph (0, 0)][DBLP]
Formal Asp. Comput., 1997, v:9, n:4, pp:395-408 [Journal] - Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. [Citation Graph (0, 0)][DBLP]
Fundam. Inform., 2006, v:70, n:1-2, pp:21-48 [Journal] - Mark B. Josephs
The Data Refinement Calculator for Z Specifications. [Citation Graph (0, 0)][DBLP]
Inf. Process. Lett., 1988, v:27, n:1, pp:29-33 [Journal] - Hemangee K. Kapoor, Mark B. Josephs
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench. [Citation Graph (0, 0)][DBLP]
Inf. Process. Lett., 2004, v:89, n:6, pp:293-296 [Journal] - Mark B. Josephs
Functional Programming with Side-Effects. [Citation Graph (0, 0)][DBLP]
Sci. Comput. Program., 1986, v:7, n:3, pp:279-296 [Journal] - Mark B. Josephs
Protocol Specification, Testing and Verification XV, by Piotr Dembinski and Marek Sredniawa (Editors), Chapman and Hall, 1996 (Book Review). [Citation Graph (0, 0)][DBLP]
Softw. Test., Verif. Reliab., 1998, v:8, n:1, pp:49- [Journal] - Mark B. Josephs
The Semantics of Lazy Functional Languages. [Citation Graph (0, 0)][DBLP]
Theor. Comput. Sci., 1989, v:68, n:1, pp:105-111 [Journal] - Mark B. Josephs, Hemangee K. Kapoor
Controllable Delay-Insensitive Processes. [Citation Graph (0, 0)][DBLP]
Fundam. Inform., 2007, v:78, n:1, pp:101-130 [Journal] - Mark B. Josephs, Jelio T. Yantchev
CMOS design of the tree arbiter element. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:472-476 [Journal]
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