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Muhammad Shafique: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. M. R. K. Krishna Rao, Muhammad Shafique, Kanaan A. Faisal, Ahmed Bagais
    Infusing Critical Thinking Skill Compare and Contrast into Content of Data Structures Course. [Citation Graph (0, 0)][DBLP]
    FECS, 2006, pp:53-59 [Conf]
  2. Muhammad Shafique, M. R. K. Krishna Rao
    Infusing Parts-whole Relationship Critical Thinking Skill into Basic Computer Science Education. [Citation Graph (0, 0)][DBLP]
    FECS, 2006, pp:287-292 [Conf]
  3. Lars Bauer, Muhammad Shafique, Simon Kramer 0002, Jörg Henkel
    RISPP: Rotating Instruction Set Processing Platform. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:791-796 [Conf]
  4. Ibrahim M. Al-Harazin, Muhammad Shafique, Jarallah S. Al-Ghamdi, Muhammed S. Al-Mulhem
    Visualization taxonomy for software metrics. [Citation Graph (0, 0)][DBLP]
    SEDE, 2007, pp:356-362 [Conf]
  5. Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel
    A Self-Adaptive Extensible Embedded Processor. [Citation Graph (0, 0)][DBLP]
    SASO, 2007, pp:344-350 [Conf]
  6. David E. Dodds, Muhammad Shafique, Bernardo Celaya
    TDR and FDR Identification of Bad Splices in Telephone Cables. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:838-841 [Conf]
  7. M. R. K. Krishna Rao, S. Junaidu, Talal Maghrabi, Muhammad Shafique, M. Ahmed, Kanaan A. Faisal
    Principles of curriculum design and revision: a case study in implementing computing curricula CC2001. [Citation Graph (0, 0)][DBLP]
    ITiCSE, 2005, pp:256-260 [Conf]

  8. MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. [Citation Graph (, )][DBLP]

  9. Run-time instruction set selection in a transmutable embedded processor. [Citation Graph (, )][DBLP]

  10. Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. [Citation Graph (, )][DBLP]

  11. Cross-architectural design space exploration tool for reconfigurable processors. [Citation Graph (, )][DBLP]

  12. A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. [Citation Graph (, )][DBLP]

  13. KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. [Citation Graph (, )][DBLP]

  14. enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. [Citation Graph (, )][DBLP]

  15. An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion. [Citation Graph (, )][DBLP]

  16. An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms. [Citation Graph (, )][DBLP]

  17. Infusing Critical Thinking Skill Classification into a Software Engineering Course. [Citation Graph (, )][DBLP]

  18. A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. [Citation Graph (, )][DBLP]

  19. RISPP: A run-time adaptive reconfigurable embedded processor. [Citation Graph (, )][DBLP]

  20. REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. [Citation Graph (, )][DBLP]

  21. Non-linear rate control for H.264/AVC video encoder with multiple picture types using image-statistics and motion-based Macroblock Prioritization. [Citation Graph (, )][DBLP]

  22. 3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. [Citation Graph (, )][DBLP]

  23. finGAD: A Jar File Fingerprint Generator and Detector. [Citation Graph (, )][DBLP]

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