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Henrik Hulgaard :
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Jesper B. Møller , Henrik Hulgaard , Henrik Reif Andersen Timed Verification of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP ] Concurrency and Hardware Design, 2002, pp:274-312 [Conf ] Tod Amon , Henrik Hulgaard Symbolic Time Separation of Events. [Citation Graph (0, 0)][DBLP ] ASYNC, 1999, pp:83-93 [Conf ] Henrik Hulgaard , Steven M. Burns Efficient Timing Analysis of a Class of Petri Nets. [Citation Graph (0, 0)][DBLP ] CAV, 1995, pp:423-436 [Conf ] Jesper B. Møller , Jakob Lichtenberg , Henrik Reif Andersen , Henrik Hulgaard Difference Decision Diagrams. [Citation Graph (0, 0)][DBLP ] CSL, 1999, pp:111-125 [Conf ] Fen Jin , Henrik Hulgaard , Eduard Cerny Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints. [Citation Graph (0, 0)][DBLP ] FMCAD, 1998, pp:167-184 [Conf ] Henrik Hulgaard , Per H. Christensen , Jørgen Staunstrup Synthesizing Delay Insensitive Circuits from Verified Programs. [Citation Graph (0, 0)][DBLP ] Research Directions in High-Level Parallel Programming Languages, 1991, pp:326-337 [Conf ] Henrik Hulgaard , Steven M. Burns , Tod Amon , Gaetano Borriello Practical applications of an efficient time separation of events algorithm. [Citation Graph (0, 0)][DBLP ] ICCAD, 1993, pp:146-151 [Conf ] Tod Amon , Henrik Hulgaard , Steven M. Burns , Gaetano Borriello An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. [Citation Graph (0, 0)][DBLP ] ICCD, 1993, pp:166-173 [Conf ] Henrik Reif Andersen , Henrik Hulgaard Boolean Expression Diagrams (Extended Abstract). [Citation Graph (0, 0)][DBLP ] LICS, 1997, pp:88-98 [Conf ] Gerd Behrmann , Kim Guldstrand Larsen , Henrik Reif Andersen , Henrik Hulgaard , Jørn Lind-Nielsen Verification of Hierarchical State/Event Systems Using Reusability and Compositionality. [Citation Graph (0, 0)][DBLP ] TACAS, 1999, pp:163-177 [Conf ] Jørn Lind-Nielsen , Henrik Reif Andersen , Gerd Behrmann , Henrik Hulgaard , Kåre J. Kristoffersen , Kim Guldstrand Larsen Verification of Large State/Event Systems Using Compositionality and Dependency Analysis. [Citation Graph (0, 0)][DBLP ] TACAS, 1998, pp:201-216 [Conf ] Poul Frederick Williams , Henrik Reif Andersen , Henrik Hulgaard Satisfiability Checking Using Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP ] TACAS, 2001, pp:39-51 [Conf ] Jørgen Staunstrup , Henrik Reif Andersen , Henrik Hulgaard , Jørn Lind-Nielsen , Kim Guldstrand Larsen , Gerd Behrmann , Kåre J. Kristoffersen , Arne Skou , Henrik Leerberg , Niels Bo Theilgaard Practical Verification of Embedded Software. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 2000, v:33, n:5, pp:68-75 [Journal ] Jesper B. Møller , Jakob Lichtenberg , Henrik Reif Andersen , Henrik Hulgaard Fully Symbolic Model Checking of Timed Systems using Difference Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal ] Gerd Behrmann , Kim Guldstrand Larsen , Henrik Reif Andersen , Henrik Hulgaard , Jørn Lind-Nielsen Verification of Hierarchical State/Event Systems using Reusability and Compositionality. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2002, v:21, n:2, pp:225-244 [Journal ] Henrik Hulgaard , Steven M. Burns Bounded Delay Timing Analysis of a Class of CSP Programs. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 1997, v:11, n:3, pp:265-294 [Journal ] Jørn Lind-Nielsen , Henrik Reif Andersen , Henrik Hulgaard , Gerd Behrmann , Kåre J. Kristoffersen , Kim Guldstrand Larsen Verification of Large State/Event Systems Using Compositionality and Dependency Analysis. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2001, v:18, n:1, pp:5-23 [Journal ] Henrik Reif Andersen , Henrik Hulgaard Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP ] Inf. Comput., 2002, v:179, n:2, pp:194-212 [Journal ] Jesper B. Møller , Henrik Hulgaard , Henrik Reif Andersen Symbolic model checking of timed guarded commands using difference decision diagrams. [Citation Graph (0, 0)][DBLP ] J. Log. Algebr. Program., 2002, v:52, n:, pp:53-77 [Journal ] Poul Frederick Williams , Henrik Reif Andersen , Henrik Hulgaard Satisfiability checking using Boolean Expression Diagrams. [Citation Graph (0, 0)][DBLP ] STTT, 2003, v:5, n:1, pp:4-14 [Journal ] Henrik Hulgaard , Steven M. Burns , Tod Amon , Gaetano Borriello An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1995, v:44, n:11, pp:1306-1317 [Journal ] Henrik Hulgaard , Tod Amon Symbolic timing analysis of asynchronous systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1093-1104 [Journal ] Henrik Hulgaard , Poul Frederick Williams , Henrik Reif Andersen Equivalence checking of combinational circuits using Boolean expression diagrams. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:7, pp:903-917 [Journal ] Search in 0.002secs, Finished in 0.306secs