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Publications of Author

1. Jon G. Bredeson, Paul T. Hulina
   Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits [Citation Graph (0, 0)][DBLP]
   FOCS, 1970, pp:104-108 [Conf]
   
2. Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
   A comparative evaluation of software techniques to hide memory latency. [Citation Graph (0, 0)][DBLP]
   HICSS (1), 1995, pp:229- [Conf]
   
3. Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor
   Program Balance and Its Impact on High Performance RISC Architectures. [Citation Graph (0, 0)][DBLP]
   HPCA, 1995, pp:370-379 [Conf]
   
4. David L. Landis, Paul T. Hulina, Scott Deno, Luke Roth, Lee D. Coraor
   Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. [Citation Graph (0, 0)][DBLP]
   ICCD, 1999, pp:146-151 [Conf]
   
5. Ali Berrached, Paul T. Hulina, Lee D. Coraor
   Structured Data Access Mechanisms for a Decoupled Computer Architecture. [Citation Graph (0, 0)][DBLP]
   ICPP, 1994, pp:285-289 [Conf]
   
6. Lee D. Coraor, Paul T. Hulina
   A Reconfigurable Multiprocessor. [Citation Graph (0, 0)][DBLP]
   ICPP, 1985, pp:649-651 [Conf]
   
7. Paul T. Hulina, Lee D. Coraor
   A Hardware Memory Mapping Unit for Efficient Address Computation. [Citation Graph (0, 0)][DBLP]
   ICPP, 1987, pp:340-343 [Conf]
   
8. Paul T. Hulina, Lee D. Coraor, Shih-Wei Sun
   Performance Analysis of an Address Generation Coprocessor. [Citation Graph (0, 0)][DBLP]
   ICPP (1), 1991, pp:136-143 [Conf]
   
9. Lizy Kurian John, Bermjae Choi, Paul T. Hulina, Lee D. Coraor
   Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. [Citation Graph (0, 0)][DBLP]
   ICPP (1), 1994, pp:212-219 [Conf]
   
10. Lizy Kurian John, Paul T. Hulina, Lee D. Coraor
    Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:236-245 [Conf]
    
11. Lizy Kurian John, Paul T. Hulina, Lee D. Coraor, Dhamir N. Mannai
    Classification and Performance Evaluation of Instruction Buffering Techniques. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:150-159 [Conf]
    
12. Luke Roth, Lee D. Coraor, David L. Landis, Paul T. Hulina, Scott Deno
    Computing in Memory Architectures for Digital Image Processing. [Citation Graph (0, 0)][DBLP]
    MTDT, 1999, pp:8-15 [Conf]
    
13. Scott Deno, David L. Landis, Paul T. Hulina, Sanjay Balasubramanian
    A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:222-0 [Conf]
    
14. David L. Landis, Praveen Guddeti, Paul T. Hulina, Lee D. Coraor
    Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 1999, pp:52-0 [Conf]
    
15. Paul T. Hulina, Lee D. Coraor
    Coprocessor architectures for efficient address computation and memory accessing. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 1990, v:5, n:3, pp:137-146 [Journal]
    
16. Jon G. Bredeson, Paul T. Hulina
    Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits [Citation Graph (0, 0)][DBLP]
    Information and Control, 1972, v:20, n:2, pp:114-124 [Journal]
    
17. Lee D. Coraor, Paul T. Hulina, Orlando A. Morean
    A General Model for Memory-Based Finite-State Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:2, pp:175-184 [Journal]
    
18. Lizy Kurian John, Paul T. Hulina, Lee D. Coraor
    Memory Latency Effects in Decoupled Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:10, pp:1129-1139 [Journal]