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J. Robert Jump :
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J. Robert Jump , P. S. Thiagarajan On the Equivalence of Asynchronous Control Structures [Citation Graph (0, 0)][DBLP ] FOCS, 1972, pp:212-223 [Conf ] H. A. Rizvi , James B. Sinclair , J. Robert Jump , J. Carson Execution-Driven Simulation of a Superscalar Processor. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:185-194 [Conf ] Manoj Kumar , J. Robert Jump Generalized Delta Networks. [Citation Graph (0, 0)][DBLP ] ICPP, 1983, pp:10-18 [Conf ] S. R. Ahuja , J. Robert Jump A Modular Memory Scheme for Array Processing. [Citation Graph (0, 0)][DBLP ] ISCA, 1977, pp:90-94 [Conf ] David T. Harper III , J. Robert Jump Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme. [Citation Graph (0, 0)][DBLP ] ISCA, 1986, pp:324-328 [Conf ] David T. Harper III , J. Robert Jump Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] ISCA, 1987, pp:171-175 [Conf ] Manoj Kumar , Daniel M. Dias , J. Robert Jump Switching Strategies in a Class of Packet Switching Networks [Citation Graph (0, 0)][DBLP ] ISCA, 1983, pp:284-300 [Conf ] G. Wolf , J. Robert Jump Matrix Multiplication in an Interleaved Array Processing Architecture. [Citation Graph (0, 0)][DBLP ] ISCA, 1985, pp:11-17 [Conf ] Sandhya Dwarkadas , J. Robert Jump , R. Mukherjee , James B. Sinclair Execution-Driven Simulation of Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] MASCOTS, 1993, pp:83-86 [Conf ] J. Robert Jump , Sridhar Lakshmanamurthy NETSIM: A General-Purpose Interconnection Network Simulator. [Citation Graph (0, 0)][DBLP ] MASCOTS, 1993, pp:121-125 [Conf ] R. C. Covington , Sridhar Madala , V. Mehta , J. Robert Jump , James B. Sinclair The Rice Parallel Processing Testbed. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 1988, pp:4-11 [Conf ] W. P. Dawkins , V. Debbad , J. Robert Jump , James B. Sinclair Efficient Simulation of Multiprogramming. [Citation Graph (0, 0)][DBLP ] SIGMETRICS, 1990, pp:237-238 [Conf ] Sandhya Dwarkadas , J. Robert Jump , James B. Sinclair Efficient simulation of cache memories. [Citation Graph (0, 0)][DBLP ] Winter Simulation Conference, 1989, pp:1032-1041 [Conf ] Daniel M. Dias , J. Robert Jump Packet Switching Interconnection Networks for Modular Systems. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1981, v:14, n:12, pp:43-53 [Journal ] Susan E. Conry , J. Robert Jump On Functional Equivalences in a Model for Parallel Computation [Citation Graph (0, 0)][DBLP ] Information and Control, 1979, v:41, n:3, pp:247-274 [Journal ] N. D. Jotwani , J. Robert Jump Top-Down Design in the Context of Parallel Programs [Citation Graph (0, 0)][DBLP ] Information and Control, 1979, v:40, n:3, pp:241-257 [Journal ] J. Robert Jump A Note on the Iterative Decomposition of Finite Automata [Citation Graph (0, 0)][DBLP ] Information and Control, 1969, v:15, n:5, pp:424-435 [Journal ] J. Robert Jump , Jayang S. Kirtane On the Interconnection Structure of Cellular Networks [Citation Graph (0, 0)][DBLP ] Information and Control, 1974, v:24, n:1, pp:74-91 [Journal ] J. Robert Jump , Shreehari Marathe On the Length of Feedback Shift Registers [Citation Graph (0, 0)][DBLP ] Information and Control, 1971, v:19, n:4, pp:345-352 [Journal ] R. G. Convington , Sandhya Dwarkadas , J. Robert Jump , James B. Sinclair , Sridhar Madala Efficient Simulation of Parallel Computer Systems. [Citation Graph (0, 0)][DBLP ] International Journal in Computer Simulation, 1991, v:1, n:1, pp:- [Journal ] J. Robert Jump , P. S. Thiagarajan On the Interconnection of Asynchronous Control Structures. [Citation Graph (0, 0)][DBLP ] J. ACM, 1975, v:22, n:4, pp:596-612 [Journal ] David T. Harper III , J. Robert Jump Evaluation of Reduced Bandwidth Multistage Networks. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1990, v:9, n:3, pp:304-311 [Journal ] J. Robert Jump , P. S. Thiagarajan On the Equivalence of Asynchronous Control Structures. [Citation Graph (0, 0)][DBLP ] SIAM J. Comput., 1973, v:2, n:2, pp:67-87 [Journal ] Daniel M. Dias , J. Robert Jump Analysis and Simulation of Buffered Delta Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1981, v:30, n:4, pp:273-282 [Journal ] David T. Harper III , J. Robert Jump Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1987, v:36, n:12, pp:1440-1449 [Journal ] J. Robert Jump , Sudhir Ahuja Effective Pipelining of Digital Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1978, v:27, n:9, pp:855-865 [Journal ] Manoj Kumar , Daniel M. Dias , J. Robert Jump Switching Strategies in Shuffle-Exchange Packet-Switched Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1985, v:34, n:2, pp:180-186 [Journal ] Manoj Kumar , J. Robert Jump Performance of Unbuffered Shuffle-Exchange Networks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1986, v:35, n:6, pp:573-578 [Journal ] Sandhya Dwarkadas , J. Robert Jump , James B. Sinclair Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis. [Citation Graph (0, 0)][DBLP ] ACM Trans. Model. Comput. Simul., 1994, v:4, n:4, pp:314-338 [Journal ] An interleaved array-processing architecture. [Citation Graph (, )][DBLP ] Augmented and pruned n log n multistaged networks: topology and performance. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.304secs