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## Search the dblp DataBase
Zdenek Hanzálek:
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## Publications of Author- Libor Waszniowski, Zdenek Hanzálek
**Analysis of Real Time Operating System Based Applications.**[Citation Graph (0, 0)][DBLP] FORMATS, 2003, pp:219-233 [Conf] - Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek
**Performance Tuning of Iterative Algorithms in Signal Processing.**[Citation Graph (0, 0)][DBLP] FPL, 2005, pp:699-702 [Conf] - Zdenek Hanzálek
**Simulating Neural Networks on Telmat T-node.**[Citation Graph (0, 0)][DBLP] HPCN, 1994, pp:416-417 [Conf] - Premysl Sucha, Zdenek Hanzálek
**Scheduling of tasks with precedence delays and relative deadlines framework for time-optimal dynamic reconfiguration of FPGAs.**[Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf] - Premysl Sucha, Zdenek Hanzálek
**Scheduling of Tasks with Precedence Delays and Relative Deadlines - Framework for Time-optimal Dynamic Reconfiguration of FPGAs.**[Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:1-8 [Conf] - Ondrej Dolejs, Zdenek Hanzálek
**Optimality of the Tree Building Control Protocol.**[Citation Graph (0, 0)][DBLP] PDPTA, 2002, pp:1685-1691 [Conf] - Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek
**Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit.**[Citation Graph (0, 0)][DBLP] IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:404-412 [Conf] - Martina Svadova, Zdenek Hanzálek
**An algorithm for the evolution graph of extended hybrid Petri nets.**[Citation Graph (0, 0)][DBLP] SMC (5), 2004, pp:4905-4910 [Conf] - Zdenek Hanzálek
**A Parallel Algorithm for Gradient Training of Feedforward Neural Networks.**[Citation Graph (0, 0)][DBLP] Parallel Computing, 1998, v:24, n:5-6, pp:823-839 [Journal] - Roman Bartosinski, Zdenek Hanzálek, Petr Struzka, Libor Waszniowski
**Integrated Environment for Embedded Control Systems Design.**[Citation Graph (0, 0)][DBLP] IPDPS, 2007, pp:1-8 [Conf] - Roman Bartosinski, Zdenek Hanzálek, Libor Waszniowski, Petr Struzka
**Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development.**[Citation Graph (0, 0)][DBLP] ETFA, 2006, pp:625-628 [Conf] - Ondrej Spinka, Jan Krakora, Michal Sojka, Zdenek Hanzálek
**Los-Cost Avionics System for Ultra-Light Aircrafts.**[Citation Graph (0, 0)][DBLP] ETFA, 2006, pp:102-109 [Conf] - Premysl Sucha, Zdenek Hanzálek, Antonin Hermanek, Jan Schier
**Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design - Implementation of Finite Interval Constant Modulus Algorithm.**[Citation Graph (0, 0)][DBLP] VLSI Signal Processing, 2007, v:46, n:1, pp:35-53 [Journal] **Profinet IO IRT Message Scheduling.**[Citation Graph (, )][DBLP]**Feeder Setup Optimization in SMT Assembly.**[Citation Graph (, )][DBLP]**A Simulation Model for the IEEE 802.15.4 protocol: Delay/Throughput Evaluation of the GTS Mechanism.**[Citation Graph (, )][DBLP]**Modular architecture for real-time contract-based framework.**[Citation Graph (, )][DBLP]
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