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Ilan Y. Spillinger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
    Architectural Improvements for Data-Driven VLSI Processing Arrays. [Citation Graph (0, 0)][DBLP]
    FPCA, 1989, pp:243-259 [Conf]
  2. Gideon D. Intrater, Ilan Y. Spillinger
    Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. [Citation Graph (0, 0)][DBLP]
    ISCA, 1992, pp:106-113 [Conf]
  3. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 1: Concepts and Coverage Metrics. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:857-866 [Conf]
  4. Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
    Delay Test Generation 2: Algebra and Algorithms. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:867-876 [Conf]
  5. Gabriel M. Silberman, Ilan Y. Spillinger
    The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:332-339 [Conf]
  6. Gabriel M. Silberman, Ilan Y. Spillinger
    G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:764-772 [Conf]
  7. Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger
    Whistle: A Workbench for Test Development of Library-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1989, v:22, n:4, pp:27-41 [Journal]
  8. Ilan Y. Spillinger, Chris J. Newburn
    Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  9. Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
    Architectural Improvement for a Data-Driven VLSI Processing Array. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:4, pp:308-322 [Journal]
  10. Gideon D. Intrater, Ilan Y. Spillinger
    Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:10, pp:1140-1150 [Journal]
  11. Gabriel M. Silberman, Ilan Y. Spillinger
    Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:66-79 [Journal]
  12. Gabriel M. Silberman, Ilan Y. Spillinger
    RIDDLE: A Foundation for Test Generation on a High-Level Design Description. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:1, pp:80-87 [Journal]
  13. Guy Even, Ilan Y. Spillinger, Leon Stok
    Retiming revisited and reversed. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:3, pp:348-357 [Journal]
  14. Gabriel M. Silberman, Ilan Y. Spillinger
    Using functional fault simulation and the difference fault model to estimate implementation fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1335-1343 [Journal]
  15. Ilan Y. Spillinger, Gabriel M. Silberman
    Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:3, pp:396-404 [Journal]

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