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Paul Berube: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Paul Berube, José Nelson Amaral, Mike MacGregor
    An FPGA prototype for the experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:253- [Conf]
  2. Paul Berube, Ashley Zinyk, José Nelson Amaral, Mike MacGregor
    The Bank Nth Chance Replacement Policy for FPGA-Based CAMs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:648-660 [Conf]
  3. Soraya Kasnavi, Paul Berube, Vincent C. Gaudet, José Nelson Amaral
    A Multizone Pipelined Cache for IP Routing. [Citation Graph (0, 0)][DBLP]
    NETWORKING, 2005, pp:574-585 [Conf]
  4. Paul Berube, Mike MacGregor, José Nelson Amaral
    FPGA implementation and experimental evaluation of a multizone network cache. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:237-252 [Journal]
  5. Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati
    Evaluation of Offset Assignment Heuristics. [Citation Graph (0, 0)][DBLP]
    HiPEAC, 2007, pp:261-275 [Conf]

  6. Workload Reduction for Multi-input Feedback-Directed Optimization. [Citation Graph (, )][DBLP]


  7. A hardware-based longest prefix matching scheme for TCAMs. [Citation Graph (, )][DBLP]


  8. Aestimo: a feedback-directed optimization evaluation tool. [Citation Graph (, )][DBLP]


  9. A cache-based internet protocol address lookup architecture. [Citation Graph (, )][DBLP]


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