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Vaughn Betz :
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Vaughn Betz , Jonathan Rose Automatic generation of FPGA routing architectures from high-level descriptions. [Citation Graph (0, 0)][DBLP ] FPGA, 2000, pp:175-184 [Conf ] Vaughn Betz , Jonathan Rose Using Architectural ``Families'' to Increase FPGA Speed and Density. [Citation Graph (0, 0)][DBLP ] FPGA, 1995, pp:10-16 [Conf ] Vaughn Betz , Jonathan Rose FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. [Citation Graph (0, 0)][DBLP ] FPGA, 1999, pp:59-68 [Conf ] David M. Lewis , Vaughn Betz , David Jefferson , Andy Lee , Christopher Lane , Paul Leventis , Sandy Marquardt , Cameron McClintock , Bruce Pedersen , Giles Powell , Srinivas Reddy , Chris Wysocki , Richard Cliff , Jonathan Rose The StratixTM routing and logic architecture. [Citation Graph (0, 0)][DBLP ] FPGA, 2003, pp:12-20 [Conf ] David M. Lewis , Elias Ahmed , Gregg Baeckler , Vaughn Betz , Mark Bourgeault , David Cashman , David R. Galloway , Mike Hutton , Christopher Lane , Andy Lee , Paul Leventis , Sandy Marquardt , Cameron McClintock , Ketan Padalia , Bruce Pedersen , Giles Powell , Boris Ratchev , Srinivas Reddy , Jay Schleicher , Kevin Stevens , Richard Yuan , Richard Cliff , Jonathan Rose The Stratix II logic and routing architecture. [Citation Graph (0, 0)][DBLP ] FPGA, 2005, pp:14-20 [Conf ] Alexander Marquardt , Vaughn Betz , Jonathan Rose Timing-driven placement for FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 2000, pp:203-213 [Conf ] Alexander Marquardt , Vaughn Betz , Jonathan Rose Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. [Citation Graph (0, 0)][DBLP ] FPGA, 1999, pp:37-46 [Conf ] Jordan S. Swartz , Vaughn Betz , Jonathan Rose A Fast Routability-Driven Router for FPGAs. [Citation Graph (0, 0)][DBLP ] FPGA, 1998, pp:140-149 [Conf ] Russell Tessier , Vaughn Betz , David Neto , Thiagaraja Gopalsamy Power-aware RAM mapping for FPGA embedded memory blocks. [Citation Graph (0, 0)][DBLP ] FPGA, 2006, pp:189-198 [Conf ] Vaughn Betz , Jonathan Rose VPR: A new packing, placement and routing tool for FPGA research. [Citation Graph (0, 0)][DBLP ] FPL, 1997, pp:213-222 [Conf ] Vaughn Betz , Jonathan Rose Directional bias and non-uniformity in FPGA global routing architectures. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:652-659 [Conf ] R. Fung , V. Betz , W. Chow Simultaneous short-path and long-path timing optimization for FPGAs. [Citation Graph (0, 0)][DBLP ] ICCAD, 2004, pp:838-845 [Conf ] Vaughn Betz , Jonathan Rose How Much Logic Should Go in an FPGA Logic Block? [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 1998, v:15, n:1, pp:10-15 [Journal ] Vaughn Betz , Jonathan Rose Effect of the prefabricated routing track distribution on FPGA area-efficiency. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:445-456 [Journal ] Alexander Marquardt , Vaughn Betz , Jonathan Rose Speed and area tradeoffs in cluster-based FPGA architectures. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:84-93 [Journal ] High-quality, deterministic parallel placement for FPGAs on commodity hardware. [Citation Graph (, )][DBLP ] A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs. [Citation Graph (, )][DBLP ] FPGA challenges and opportunities at 40nm and beyond. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.002secs