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Erik Chmelar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Erik Chmelar
    Subframe multiplexing for FPGA manufacturing test configuration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:245- [Conf]
  2. Erik Chmelar
    Minimizing the number of test configurations for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:899-902 [Conf]
  3. Erik Chmelar
    FPGA Interconnect Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1239-1247 [Conf]
  4. Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuck
    Segmented Addressable Scan Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:405-411 [Conf]
  5. Erik Chmelar, Edward J. McCluskey
    Session Abstract. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:156-157 [Conf]
  6. Erik Chmelar, Shahin Toutounchi
    FPGA Bridging Fault Detection and Location via Differential I{DDQ}. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:109-116 [Conf]

  7. Inconsistent Fail due to Limited Tester Timing Accuracy. [Citation Graph (, )][DBLP]

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