The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Takenori Kouda: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Takenori Kouda, Yahiko Kambayashi
    FPGA Circuit Optimization Based on Block Integration (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:257- [Conf]
  2. Takenori Kouda, Yahiko Kambayashi
    FPGA circuit optimization using block integration based on multiple output capability. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1999, v:30, n:11, pp:12-21 [Journal]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002