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Baher Haroun :
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Baher Haroun , Behzad Sajjadi Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses. [Citation Graph (0, 0)][DBLP ] FPGA, 1995, pp:75-81 [Conf ] F. Rouatbi , Baher Haroun , Asim J. Al-Khalili Power estimation tool for sub-micron CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1992, pp:204-209 [Conf ] Baher Haroun , Behzard Sajjadi Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:587-589 [Conf ] Baher Haroun , Elie Torbey Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:174-178 [Conf ] Reza Golshan , Baher Haroun A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:351-354 [Conf ] Baher Haroun , Chao Hua Wu A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:9-12 [Conf ] Abdelhakim Safir , Baher Haroun , Krishnaiyan Thulasiraman A Floorplanner driven by Structural & Timing Constraints. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:157-160 [Conf ] Abdelhakim Safir , Baher Haroun , Krishnaiyan Thulasiraman Floorplanning with Datapath Optimization. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:41-44 [Conf ] Prasun Raha , Scott Randall , Richard Jennings , Bob Helmick , Ajith Amerasekera , Baher Haroun A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. [Citation Graph (0, 0)][DBLP ] ISQED, 2002, pp:148-0 [Conf ] Baher Haroun , Mohamed I. Elmasry Architectural synthesis for DSP silicon compilers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:431-447 [Journal ] Search in 0.001secs, Finished in 0.002secs