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Julien Lamoureux: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Julien Lamoureux, Steven J. E. Wilton
    FPGA clock network architecture: flexibility vs. area and power. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:101-108 [Conf]
  2. Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
    GlitchLess: an active glitch minimization technique for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:156-165 [Conf]
  3. Julien Lamoureux, Steven J. E. Wilton
    On the Interaction Between Power-Aware FPGA CAD Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:701-708 [Conf]
  4. Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux
    Fast and low-power inner product processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:646-649 [Conf]
  5. Steven J. E. Wilton, Christopher W. Jones, Julien Lamoureux
    An embedded flexible content-addressable memory core for inclusion in a Field-Programmable Gate Array. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:885-888 [Conf]
  6. Julien Lamoureux, Steven J. E. Wilton
    Architecture and CAD for FPGA Clock Networks. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
  7. Julien Lamoureux, Steven J. E. Wilton
    Activity Estimation for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  8. Julien Lamoureux, Steven J. E. Wilton
    On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:119-132 [Journal]

  9. Accelerating a Virtual Ecology Model with FPGAs. [Citation Graph (, )][DBLP]


  10. Fine-grained vs. coarse-grained shift-and-add arithmetic in FPGAs (abstract only). [Citation Graph (, )][DBLP]


  11. Clock-Aware Placement for FPGAs. [Citation Graph (, )][DBLP]


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