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Benton H. Calhoun: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Frank Honoré, Benton H. Calhoun, Anantha Chandrakasan
    Power-aware architectures and circuits for FPGA-based signal processing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:244- [Conf]
  2. Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun
    Analyzing and modeling process balance for sub-threshold circuit design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:275-280 [Conf]
  3. Benton H. Calhoun, Anantha Chandrakasan
    Characterizing and modeling minimum energy operation for subthreshold circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:90-95 [Conf]
  4. Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan
    Design methodology for fine-grained leakage control in MTCMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:104-109 [Conf]
  5. Benton H. Calhoun, Alice Wang, Naveen Verma, Anantha Chandrakasan
    Sub-threshold design: the challenges of minimizing circuit energy. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:366-368 [Conf]
  6. David D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha Chandrakasan
    Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:361-0 [Conf]
  7. Benton H. Calhoun, Denis C. Daly, Naveen Verma, Daniel F. Finchelstein, David D. Wentzloff, Alice Wang, Seong-Hwan Cho, Anantha P. Chandrakasan
    Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:6, pp:727-740 [Journal]

  8. Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. [Citation Graph (, )][DBLP]


  9. SRAM-based NBTI/PBTI sensor system design. [Citation Graph (, )][DBLP]


  10. Power switch characterization for fine-grained dynamic voltage scaling. [Citation Graph (, )][DBLP]


  11. Analyzing static and dynamic write margin for nanometer SRAMs. [Citation Graph (, )][DBLP]


  12. Serial sub-threshold circuits for ultra-low-power systems. [Citation Graph (, )][DBLP]


  13. A 2.6 µW sub-threshold mixed-signal ECG SoC. [Citation Graph (, )][DBLP]


  14. Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-Threshold Operation. [Citation Graph (, )][DBLP]


  15. Limits of bias based assist methods in nano-scale 6T SRAM. [Citation Graph (, )][DBLP]


  16. Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. [Citation Graph (, )][DBLP]


  17. Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. [Citation Graph (, )][DBLP]


  18. Body Area Sensor Networks: Challenges and Opportunities. [Citation Graph (, )][DBLP]


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