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Publications of Author

1. Mike Hutton, David Karchmer, Bryan Archell, Jason Govig
   Efficient static timing analysis and applications using edge masks. [Citation Graph (0, 0)][DBLP]
   FPGA, 2005, pp:174-183 [Conf]
   
2. David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
   The Stratix II logic and routing architecture. [Citation Graph (0, 0)][DBLP]
   FPGA, 2005, pp:14-20 [Conf]
   
3. Paul Chow, Mike Hutton
   Integrating FPGAs in high-performance computing: introduction. [Citation Graph (0, 0)][DBLP]
   FPGA, 2007, pp:131- [Conf]
   
4. Boris Ratchev, Mike Hutton, David Mendel
   Coping With Uncertainty in FPGA Architecture Design. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:662-665 [Conf]
   
5. Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald Graham, Mike Hutton, Chung-Kuan Cheng
   Timing model reduction for hierarchical timing analysis. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:415-422 [Conf]
   
6. Lei He, Mike Hutton, Tim Tuan, Steve Wilton
   Challenges and opportunities for low power FPGAs in nanometer technologies. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2005, pp:90- [Conf]
   
7. Mike Hutton
   Advances and trends in FPGA design. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2004, pp:8- [Conf]
   
8. Mike Hutton
   Architecture and CAD for FPGAs. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2004, pp:3- [Conf]
   
9. Joachim Pistorius, Mike Hutton
   Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. [Citation Graph (0, 0)][DBLP]
   SLIP, 2003, pp:31-38 [Conf]
   
10. Mike Hutton
    FPGA Architecture Design Methodology. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1- [Conf]
    
11. Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton
    FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
    
12. Mike Hutton, Yan Lin, Lei He
    Placement and Timing for FPGAs Considering Variations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-7 [Conf]
    
13. 
    An FPGA Based Memory Efficient Shared Buffer Implementation. [Citation Graph (, )][DBLP]
    
    
14. 
    Equivalence Verification of FPGA and Structured ASIC Implementations. [Citation Graph (, )][DBLP]
    
    
15. 
    Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. [Citation Graph (, )][DBLP]