The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Ninh Ngo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff
    A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:256- [Conf]
  2. J. Turner, Richard Cliff, W. Leong, Cameron McClintock, Ninh Ngo, K. Nguyen, C. K. Sung, B. Wang, J. Watson
    Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:15-20 [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002