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Zdenek Pohl: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko
    Lattice adaptive filter implementation for FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:246- [Conf]
  2. Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
    Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:262- [Conf]
  3. Antonin Hermanek, Zdenek Pohl, Jiri Kadlec
    FPGA Implementation of the Adpaptive Lattice Filter. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1095-1098 [Conf]
  4. Rudolf Matousek, Milan Tichý, Zdenek Pohl, Jiri Kadlec, Chris Softley, Nick Coleman
    Logarithmic Number System and Floating-Point Arithmetics on FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:627-636 [Conf]
  5. Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl
    Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:590-593 [Conf]
  6. Zdenek Pohl, Premysl Sucha, Jiri Kadlec, Zdenek Hanzálek
    Performance Tuning of Iterative Algorithms in Signal Processing. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:699-702 [Conf]
  7. Zdenek Pohl, Jan Schier, Miroslav Lícko, Antonin Hermanek, Milan Tichý, Rudolf Matousek, Jiri Kadlec
    Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:190- [Conf]
  8. Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek
    Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time and Embedded Technology and Applications Symposium, 2004, pp:404-412 [Conf]

  9. RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor. [Citation Graph (, )][DBLP]


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