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Garrett S. Rose: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Garrett S. Rose, Mircea R. Stan
    A programmable majority logic array using molecular scale electronics. [Citation Graph (0, 0)][DBLP]
    FPGA, 2006, pp:225- [Conf]
  2. Garrett S. Rose, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, Mircea R. Stan, John C. Bean, Lloyd R. Harriott, Yuxing Yao, James M. Tour
    Design approaches for hybrid CMOS/molecular memory based on experimental device data. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:2-7 [Conf]
  3. Nadine Gergel-Hackett, Garrett S. Rose, Peter Paliwoda, Christina A. Hacker, Curt A. Richter
    On-chip characterization of molecular electronic devices using CMOS: the design and simulation of a hybrid circuit based on experimental molecular electronic device results. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:108-113 [Conf]
  4. Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler
    Hybrid CMOS/Molecular Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:703-708 [Conf]
  5. Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan
    Large-signal two-terminal device model for nanoelectronic circuit analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1201-1208 [Journal]
  6. Garrett S. Rose, Yuxing Yao, James M. Tour, Adam C. Cabe, Nadine Gergel-Hackett, Nabanita Majumdar, John C. Bean, Lloyd R. Harriott, Mircea R. Stan
    Designing CMOS/molecular memories while considering device parameter variations. [Citation Graph (0, 0)][DBLP]
    JETC, 2007, v:3, n:1, pp:- [Journal]

  7. A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays. [Citation Graph (, )][DBLP]


  8. A dual-MOSFET equivalent resistor thermal sensor. [Citation Graph (, )][DBLP]


  9. Design considerations for variation tolerant multilevel CMOS/Nano memristor memory. [Citation Graph (, )][DBLP]


  10. The effects of logic partitioning in a majority logic based CMOS-NANO FPGA. [Citation Graph (, )][DBLP]


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