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Debasish Das: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Somsubhra Mondal, Seda Ogrenci Memik, Debasish Das
    Hierarchical LUT structures for leakage power reduction (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:272- [Conf]
  2. Debasish Das, Ahmed Shebaita, Yehea I. Ismail, Hai Zhou, Kip Killpack
    NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:25-30 [Conf]
  3. Debasish Das, Bhabani P. Sinha
    Multi-Mesh-an efficient topology for parallel processing. [Citation Graph (0, 0)][DBLP]
    IPPS, 1995, pp:17-21 [Conf]
  4. Debasish Das, Mallika De, Bhabani P. Sinha
    A New Network Topology with Multiple Meshes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:5, pp:536-551 [Journal]
  5. Debasish Das, Krishnendu Mukhopadhyaya, Bhabani P. Sinha
    Implementation of Four Common Functions on an LNS Co-Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:1, pp:155-161 [Journal]
  6. Mallika De, Debasish Das, Mabhin Ghosh, Bhabani P. Sinha
    An Efficient Sorting Algorithm on the Multi-Mesh Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:10, pp:1132-1136 [Journal]

  7. Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. [Citation Graph (, )][DBLP]

  8. Regression Learning with Multiple Noisy Oracles. [Citation Graph (, )][DBLP]

  9. Gate sizing by Lagrangian relaxation revisited. [Citation Graph (, )][DBLP]

  10. FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling. [Citation Graph (, )][DBLP]

  11. Active Selection of Sensor Sites in Remote Sensing Applications. [Citation Graph (, )][DBLP]

  12. An efficient current-based logic cell model for crosstalk delay analysis. [Citation Graph (, )][DBLP]

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