Search the dblp DataBase

Publications of Author

1. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
   A multilevel hierarchical interconnection structure for FPGA. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:225- [Conf]
   
2. Zied Marrakchi, Hayder Mrabet, Habib Mehrez
   Configuration tools for a new multilevel hierarchical FPGA. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:229- [Conf]
   
3. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez
   Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:675-679 [Conf]
   
4. Zied Marrakchi, Hayder Mrabet, Habib Mehrez
   A new Multilevel Hierarchical MFPGA and its suitable configuration tools. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2006, pp:263-268 [Conf]
   
5. Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot
   Implementation of Scalable Embedded FPGA for SOC. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2005, pp:59-62 [Conf]
   
6. Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot
   Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2006, pp:117-123 [Conf]
   
7. Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez
   Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:243-252 [Conf]
   
8. 
   Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). [Citation Graph (, )][DBLP]
   
   
9. 
   Efficient tree topology for FPGA interconnect network. [Citation Graph (, )][DBLP]
   
   
10. 
    Application Specific FPGA Using Heterogeneous Logic Blocks. [Citation Graph (, )][DBLP]
    
    
11. 
    Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. [Citation Graph (, )][DBLP]
    
    
12. 
    The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. [Citation Graph (, )][DBLP]
    
    
13. 
    Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. [Citation Graph (, )][DBLP]