The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mehrdad Najibi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping globally asynchronous locally synchronous circuits on commercial synchronous FPGAs (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:269- [Conf]
  2. Kamran Saleh, Mehrdad Najibi, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    A novel clock generation scheme for globally asynchronous locally synchronous systems: an FPGA-validated approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:296-301 [Conf]
  3. Atabak Mahram, Mehrdad Najibi, Hossein Pedram
    An asynchronous fpga logic cell implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:176-179 [Conf]
  4. Mehrdad Najibi, Kamran Saleh, Hossein Pedram
    Using standard asic back-end for qdi asynchronous circuits: dealing with isochronic fork constraint. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:299-304 [Conf]
  5. Mehrdad Najibi, M. Salehi, Ali Afzali-Kusha, Massoud Pedram, Seid Mehdi Fakhraie, Hossein Pedram
    Dynamic voltage and frequency management based on variable update intervals for frequency setting. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:755-760 [Conf]
  6. Esmail Amini, Mehrdad Najibi, Hossein Pedram
    Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:193-199 [Conf]
  7. Mahtab Niknahad, Behnam Ghavami, Mehrdad Najibi, Hossein Pedram
    A Power Estimation Methodology for QDI Asynchronous Circuits based on High-Level Simulation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:471-472 [Conf]
  8. Mehrdad Najibi, Mahtab Niknahad, Hossein Pedram
    Performance Evaluation of Asynchronous Circuits with Choice Using Abstract Probabilistic Timed Petri Nets. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:422-427 [Conf]
  9. Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi
    Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:63-69 [Conf]
  10. Behnam Ghavami, Mahtab Niknahad, Mehrdad Najibi, Hossein Pedram
    A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:463-473 [Conf]

  11. Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. [Citation Graph (, )][DBLP]


  12. Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading. [Citation Graph (, )][DBLP]


Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002