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Taraneh Taghavi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh
    Routing algorithms: enhancing routability & enabling ECO (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:266- [Conf]
  2. Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
    Block placement to ensure channel routability. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:465-468 [Conf]
  3. Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh
    Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:148-155 [Conf]
  4. Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi
    Dragon2005: large-scale mixed-size placement tool. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:245-247 [Conf]
  5. Taraneh Taghavi, Xiaojian Yang, Bo-Kyung Choi, Maogang Wang, Majid Sarrafzadeh
    Dragon2006: blockage-aware congestion-controlling mixed-size placer. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:209-211 [Conf]
  6. Taraneh Taghavi, Ani Nahapetian, Majid Sarrafzadeh
    System Level Estimation of Interconnect Length in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:438-443 [Conf]
  7. Taraneh Taghavi, Majid Sarrafzadeh
    Hierarchical Concurrent Congestion and Wirelength Estimation in the Presence of IP Blocks. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:213-218 [Conf]
  8. Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh
    Routing algorithms: architecture driven rerouting enhancement for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  9. Taraneh Taghavi, Foad Dabiri, Ani Nahapetian, Majid Sarrafzadeh
    Tutorial on congestion prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:15-24 [Conf]

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