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Abbes Amira :
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Faycal Bensaali , Abbes Amira Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] FPL, 2004, pp:991-995 [Conf ] Abbes Amira , Ahmed Bouridane , Peter Milligan Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing. [Citation Graph (0, 0)][DBLP ] FPL, 2001, pp:101-111 [Conf ] Abbes Amira , Ahmed Bouridane , Peter Milligan , Faycal Bensaali Custom Coprocessor Based Matrix Algorithms for Image and Signal Processing. [Citation Graph (0, 0)][DBLP ] FPL, 2002, pp:730-739 [Conf ] Shrutisagar Chandrasekaran , Abbes Amira High Speed / Low Power Architectures for the Finite Radon Transform. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:450-455 [Conf ] Aziz Ahmedsaid , Abbes Amira Accelerating svd on reconficurable hardware for image denoising. [Citation Graph (0, 0)][DBLP ] ICIP, 2004, pp:259-262 [Conf ] A. Amira An FPGA based parameterisable system for discrete Hartley transforms implementation. [Citation Graph (0, 0)][DBLP ] ICIP (2), 2003, pp:567-570 [Conf ] Mohammed Ali Roula , Abbes Amira , Ahmed Bouridane , Peter Milligan , Paul Sage A novel technique for unsupervised texture segmentation. [Citation Graph (0, 0)][DBLP ] ICIP (1), 2001, pp:58-61 [Conf ] Mohammed Ali Roula , Ahmed Bouridane , Fatih Kurugollu , Abbes Amira Unsupervised segmentation of multispectral images using edge progression and cost function. [Citation Graph (0, 0)][DBLP ] ICIP (3), 2002, pp:781-784 [Conf ] Muhammad Atif Tahir , Ahmed Bouridane , Fatih Kurugollu , Abbes Amira Accelerating the computation of glcm and haralick texture features on reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] ICIP, 2004, pp:2857-2860 [Conf ] Isa Servan Uzun , Abbes Amira Design and fpga implementation of non-separable 2-d biorthogonal wavelet transforms for image/video coding. [Citation Graph (0, 0)][DBLP ] ICIP, 2004, pp:2825-2828 [Conf ] Shrutisagar Chandrasekaran , Abbes Amira An area efficient low power inner product computation for discrete orthogonal transforms. [Citation Graph (0, 0)][DBLP ] ICIP (3), 2005, pp:1024-1027 [Conf ] T. Jaber , Abbes Amira , Peter Milligan A Novel Approach for Lexical Noise Analysis and Measurement in Intelligent Information Retrieval. [Citation Graph (0, 0)][DBLP ] ICPR (3), 2006, pp:370-373 [Conf ] Muhammad Atif Tahir , Ahmed Bouridane , Fatih Kurugollu , Abbes Amira Feature Selection using Tabu Search for Improving the Classification Rate of Prostate Needle Biopsies. [Citation Graph (0, 0)][DBLP ] ICPR (2), 2004, pp:335-338 [Conf ] Mohammed Ali Roula , J. Diamond , Ahmed Bouridane , P. Miller , Abbes Amira A multispectral computer vision system for automatic grading of prostatic neoplasia. [Citation Graph (0, 0)][DBLP ] ISBI, 2002, pp:193-196 [Conf ] Aziz Ahmedsaid , Abbes Amira , Ahmed Bouridane Accelerating MUSIC method on reconfigurable hardware for source localisation. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2004, pp:369-372 [Conf ] Abbes Amira , Peter Farrell An automatic face recognition system based on wavelet transforms. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:6252-6255 [Conf ] Isa Servan Uzun , Abbes Amira Design and FPGA implementation of finite Ridgelet transform [image processing applications]. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5826-5829 [Conf ] Abbes Amira , Ahmed Bouridane , Peter Milligan An FPGA based Walsh Hadamard transforms. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2001, pp:569-572 [Conf ] Faycal Bensaali , Abbes Amira , Ahmed Bouridane An efficient architecture for color space conversion using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:265-268 [Conf ] Isa Servan Uzun , Abbes Amira , Ahmed Bouridane An efficient architecture for 1-D discrete biorthogonal wavelet transform. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:697-700 [Conf ] Faycal Bensaali , Abbes Amira Accelerating colour space conversion on reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Image Vision Comput., 2005, v:23, n:11, pp:935-942 [Journal ] Isa Servan Uzun , Abbes Amira A Fpga-based Parametrizable System for High-resolution Frequency-domain Image Filtering. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 2005, v:14, n:5, pp:895-922 [Journal ] Isa Servan Uzun , Abbes Amira Real-time 2-D wavelet transform implementation for HDTV compression. [Citation Graph (0, 0)][DBLP ] Real-Time Imaging, 2005, v:11, n:2, pp:151-165 [Journal ] Faycal Bensaali , Abbes Amira , Reza Sotudeh Floating-Point Matrix Product on FPGA. [Citation Graph (0, 0)][DBLP ] AICCSA, 2007, pp:466-473 [Conf ] S. Chandrasekaran , A. Amira FPGA Implementation and Power Modelling of the Fast Walsh Transform. [Citation Graph (0, 0)][DBLP ] FPL, 2006, pp:1-4 [Conf ] S. Chandrasekaran , A. Amira Power Reduction for FPGA Implementations : Design Optimisation and High Level Modelling. [Citation Graph (0, 0)][DBLP ] FPL, 2006, pp:1-2 [Conf ] S. Chandrasekaran , A. Amira Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix Transforms. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:3207-3210 [Conf ] Djamel Bouchaffra , Abbes Amira Feature generation and machine learning for robust multimodal biometrics. [Citation Graph (0, 0)][DBLP ] Pattern Recognition, 2008, v:41, n:3, pp:775-777 [Journal ] Djamel Bouchaffra , Abbes Amira Structural hidden Markov models for biometrics: Fusion of face and fingerprint. [Citation Graph (0, 0)][DBLP ] Pattern Recognition, 2008, v:41, n:3, pp:852-867 [Journal ] High Performance FPGA Implementation of the Mersenne Twister. [Citation Graph (, )][DBLP ] DWT/PCA Face Recognition using Automatic Coefficient Selection. [Citation Graph (, )][DBLP ] An intelligent system for pet tumour detection and quantification. [Citation Graph (, )][DBLP ] An automated volumetric segmentation system combining multiscale and statistical reasoning. [Citation Graph (, )][DBLP ] Performance evaluation of DCT and wavelet transform for LSI. [Citation Graph (, )][DBLP ] Multiresolution Hybrid Approaches for Automated Face Recognition. [Citation Graph (, )][DBLP ] A New Behavioural Power Modelling Approach for FPGA based Custom Cores. [Citation Graph (, )][DBLP ] Search in 0.006secs, Finished in 0.282secs