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Publications of Author

1. Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
   Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:965-969 [Conf]
   
2. Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
   Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:497-506 [Conf]
   
3. Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
   A Self-Reconfiguration Framework for Multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1124-1126 [Conf]
   
4. Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
   High Throughput Serpent Encryption Implementation. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:996-1000 [Conf]
   
5. Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
   Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. [Citation Graph (0, 0)][DBLP]
   MSV/AMCS, 2004, pp:17-22 [Conf]
   
6. José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
   Hardware implementation of optical flow constraint equation using FPGAs. [Citation Graph (0, 0)][DBLP]
   Computer Vision and Image Understanding, 2005, v:98, n:3, pp:462-490 [Journal]
   
7. Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
   Comparison of two designs for the multifunction vehicle bus. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:797-805 [Journal]
   
8. Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
   Multiprocessor SoPC-Core for FAT volume computation. [Citation Graph (0, 0)][DBLP]
   Microprocessors and Microsystems, 2005, v:29, n:10, pp:421-434 [Journal]
   
9. Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
   Hardware architecture for a general regression neural network coprocessor. [Citation Graph (0, 0)][DBLP]
   Neurocomputing, 2007, v:71, n:1-3, pp:78-87 [Journal]
   
10. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
    Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:629-643 [Journal]
    
11. 
    Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. [Citation Graph (, )][DBLP]
    
    
12. 
    DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. [Citation Graph (, )][DBLP]
    
    
13. 
    AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. [Citation Graph (, )][DBLP]
    
    
14. 
    Overview of FPGA-Based Multiprocessor Systems. [Citation Graph (, )][DBLP]
    
    
15. 
    PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]
    
    
16. 
    Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. [Citation Graph (, )][DBLP]