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Armando Astarloa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu
    Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:965-969 [Conf]
  2. Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
    Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:497-506 [Conf]
  3. Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
    A Self-Reconfiguration Framework for Multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1124-1126 [Conf]
  4. Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado
    High Throughput Serpent Encryption Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:996-1000 [Conf]
  5. Purificación Sáiz, Jon Matías, Eduardo Jacob, Javier Bustamante, Armando Astarloa
    Adaptation of IEEE 802.1X for Secure Session Establishment Between Ethernet Peers. [Citation Graph (0, 0)][DBLP]
    ICISS, 2006, pp:220-234 [Conf]
  6. Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
    Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. [Citation Graph (0, 0)][DBLP]
    MSV/AMCS, 2004, pp:17-22 [Conf]
  7. Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
    Multiprocessor SoPC-Core for FAT volume computation. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:10, pp:421-434 [Journal]
  8. Jesús Lázaro, Jagoba Arias, José Luis Martín, Carlos Cuadrado, Armando Astarloa
    Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:8-9, pp:375-380 [Journal]
  9. Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa
    Malguki: an RSSI based ad hoc location algorithm. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:8, pp:403-409 [Journal]
  10. Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez, Armando Astarloa
    GPS-less location algorithm for wireless sensor networks. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2007, v:30, n:14-15, pp:2904-2916 [Journal]
  11. Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
    Hardware architecture for a general regression neural network coprocessor. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:78-87 [Journal]
  12. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
    Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:9, pp:629-643 [Journal]

  13. Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. [Citation Graph (, )][DBLP]


  14. A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs. [Citation Graph (, )][DBLP]


  15. DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. [Citation Graph (, )][DBLP]


  16. AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. [Citation Graph (, )][DBLP]


  17. Overview of FPGA-Based Multiprocessor Systems. [Citation Graph (, )][DBLP]


  18. PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. [Citation Graph (, )][DBLP]


  19. Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. [Citation Graph (, )][DBLP]


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