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Spyros Blionas:
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- Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas
A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP] FPL, 2002, pp:1080-1083 [Conf]
- G. Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis
Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP] FPL, 2002, pp:1027-1036 [Conf]
- Dimitrios Soudris, Marios Kesoulis, C. Koukourlis, Adonios Thanailakis, Spyros Blionas
Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size. [Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:73-76 [Conf]
- Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis
A reusable IP FFT core for DSP applications. [Citation Graph (0, 0)][DBLP] ISCAS (3), 2004, pp:621-624 [Conf]
- Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2001, pp:334-337 [Conf]
- Christos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki
A Multi-level Validation Methodology for Wireless Network Applications. [Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:332-341 [Conf]
- Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
Energy-Aware System-on-Chip for 5 GHz Wireless LANs. [Citation Graph (0, 0)][DBLP] PATMOS, 2005, pp:166-176 [Conf]
- Spiridon Nikolaidis, Nikolaos Kavvadias, T. Laopoulos, Labros Bisdounis, Spyros Blionas
Instruction Level Energy Modeling for Pipelined Processors. [Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:279-288 [Conf]
- Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. [Citation Graph (0, 0)][DBLP] PATMOS, 2004, pp:613-622 [Conf]
- Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP] PATMOS, 2003, pp:430-439 [Conf]
- Aristodemos Pnevmatikakis, Spyros Blionas, Dimitris Triantis
Physical Layer of a Base-band Ofdm Modem: Algorithms and Performance. [Citation Graph (0, 0)][DBLP] Journal of Circuits, Systems, and Computers, 2005, v:14, n:3, pp:631-651 [Journal]
- Kostas Masselos, Antti Pelkonen, Miroslav Cupák, Spyros Blionas
Realization of wireless multimedia communication systems on reconfigurable platforms. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2003, v:49, n:4-6, pp:155-175 [Journal]
- Christos Drosos, Chrissavgi Dre, Dimitris Metafas, Dimitrios Soudris, Spyros Blionas
The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal. [Citation Graph (0, 0)][DBLP] Microelectronics Journal, 2004, v:35, n:7, pp:609-620 [Journal]
- Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:1, pp:18-26 [Journal]
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