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Kostas Masselos :
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Spyros Blionas , Kostas Masselos , Chrissavgi Dre , Christos Drosos , F. Z. Ieromnimon , T. Pagonis , A. Pneymatikakis , Anna Tatsaki , T. Trimis , A. Vontzalidis , Dimitris Metafas A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip. [Citation Graph (0, 0)][DBLP ] FPL, 2002, pp:1080-1083 [Conf ] G. Koutroumpezis , Konstantinos Tatas , Dimitrios Soudris , Spyros Blionas , Kostas Masselos , Adonios Thanailakis Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations. [Citation Graph (0, 0)][DBLP ] FPL, 2002, pp:1027-1036 [Conf ] Yang Qu , Kari Tiensyrjä , Kostas Masselos System-Level Modeling of Dynamically Reconfigurable Co-processors. [Citation Graph (0, 0)][DBLP ] FPL, 2004, pp:881-885 [Conf ] Antti Pelkonen , Kostas Masselos , Miroslav Cupák System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC. [Citation Graph (0, 0)][DBLP ] IPDPS, 2003, pp:174- [Conf ] Evaggelia Theochari , Konstantinos Tatas , Dimitrios Soudris , Kostas Masselos , Konstantinos Potamianos , Spyros Blionas , Antonios Thanailakis A reusable IP FFT core for DSP applications. [Citation Graph (0, 0)][DBLP ] ISCAS (3), 2004, pp:621-624 [Conf ] Nikolaos D. Zervas , Kostas Masselos , Odysseas G. Koufopavlou , Constantinos E. Goutis Power exploration of multimedia applications realized on embedded cores. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 1999, pp:378-381 [Conf ] Kostas Masselos , Panagiotis Merakos , Thanos Stouraitis , Constantinos E. Goutis Low power synthesis of sum-of-product computation in DSP algorithms. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 1999, pp:420-423 [Conf ] Kostas Masselos , Koen Danckaert , Francky Catthoor , Constantinos E. Goutis , Hugo De Man A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. [Citation Graph (0, 0)][DBLP ] ISLPED, 1999, pp:270-272 [Conf ] Kostas Masselos , S. Theoharis , Panagiotis Merakos , Thanos Stouraitis , Constantinos E. Goutis Low power synthesis of sum-of-products computation (poster session). [Citation Graph (0, 0)][DBLP ] ISLPED, 2000, pp:234-237 [Conf ] Kostas Masselos , Spyros Blionas , Jean-Yves Mignolet , A. Foster , Dimitrios Soudris , Spiridon Nikolaidis Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform. [Citation Graph (0, 0)][DBLP ] PATMOS, 2004, pp:613-622 [Conf ] Kostas Masselos , Panagiotis Merakos , Constantinos E. Goutis Power Efficient Vector Quantization Design Using Pixel Truncation. [Citation Graph (0, 0)][DBLP ] PATMOS, 2002, pp:409-418 [Conf ] Konstantinos Tatas , K. Siozios , Dimitrios Soudris , Adonios Thanailakis , Kostas Masselos , Konstantinos Potamianos , Spyros Blionas Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] PATMOS, 2003, pp:430-439 [Conf ] Kostas Masselos , Antti Pelkonen , Miroslav Cupák , Spyros Blionas Realization of wireless multimedia communication systems on reconfigurable platforms. [Citation Graph (0, 0)][DBLP ] Journal of Systems Architecture, 2003, v:49, n:4-6, pp:155-175 [Journal ] Kostas Masselos , Yiannis Andreopoulos , Thanos Stouraitis Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Kostas Masselos , Panagiotis Merakos , Thanos Stouraitis , Constantinos E. Goutis Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:492-497 [Journal ] Koen Danckaert , Kostas Masselos , Francky Catthoor , Hugo De Man , Constantinos E. Goutis Strategy for power-efficient design of parallel systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:258-265 [Journal ] Kostas Masselos , Francky Catthoor , Constantinos E. Goutis , Hugo De Man A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:515-518 [Journal ] Kostas Masselos , Panagiotis Merakos , S. Theoharis , Thanos Stouraitis , Constantinos E. Goutis Power efficient data path synthesis of sum-of-products computations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:446-450 [Journal ] SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.303secs