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Sameh W. Asaad: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Sameh W. Asaad, Kevin Warren
Speed Optimization of the ALR Circuit Using an FPGA with Embedded RAM: A Design Experience. [Citation Graph (0, 0)][DBLP]
FPL, 1998, pp:278-287 [Conf] - Victor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno
Design methodology for semi custom processor cores. [Citation Graph (0, 0)][DBLP]
ACM Great Lakes Symposium on VLSI, 2004, pp:448-452 [Conf] - Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno
Reducing instruction fetch energy with backwards branch control information and buffering. [Citation Graph (0, 0)][DBLP]
ISLPED, 2003, pp:322-325 [Conf] - Stephen V. Kosonocky, Arthur A. Bright, Kevin Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin Stawiasz
Designing a Testable System on a Chip. [Citation Graph (0, 0)][DBLP]
VTS, 1998, pp:2-7 [Conf] - Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter
An innovative low-power high-performance programmable signal processor for digital communications. [Citation Graph (0, 0)][DBLP]
IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:299-326 [Journal]
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