The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Antonio García: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz
    Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:531-534 [Conf]
  2. Uwe Meyer-Bäse, Javier Ramírez, Antonio García
    Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:897-904 [Conf]
  3. Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
    Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:384-393 [Conf]
  4. Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz
    Intellectual Property Protection for RNS Circuits on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1139-1141 [Conf]
  5. Javier Ramírez, Antonio García
    U. Meyer-Baese, A. Lloris: Fast RNS FPL-based Communications Receiver Design and Implementation. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:472-481 [Conf]
  6. Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
    Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:342-351 [Conf]
  7. Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz
    Design and Implementation of RNS-Based Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1135-1138 [Conf]
  8. Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, F. J. Taylor
    RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:486-489 [Conf]
  9. Miguel A. Melgarejo, Carlos Andrés Peña-Reyes, Antonio García
    Computational model and architectural proposal for a hardware type-2 fuzzy system. [Citation Graph (0, 0)][DBLP]
    Neural Networks and Computational Intelligence, 2004, pp:279-284 [Conf]
  10. Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz
    Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:657-665 [Conf]
  11. Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz
    A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:188-197 [Conf]
  12. Alberto Díaz, Pablo Gervás, Antonio García
    Evaluation of a System for Personalized Summarization of Web Contents. [Citation Graph (0, 0)][DBLP]
    User Modeling, 2005, pp:453-462 [Conf]
  13. Javier Ramírez, Antonio García
    A Fast QRNS-Based Algorithm for the DCT and Its Field-Programmable Logic Implementation. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:111-0 [Journal]
  14. Javier Ramírez, Uwe Meyer-Bäse, Antonio García
    Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:1, pp:165-177 [Journal]
  15. Antonio García, Antonio Lloris-Ruíz
    A Look-Up Scheme for Scaling in the RNS. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:7, pp:748-751 [Journal]
  16. Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris, Uwe Meyer-Bäse
    IPP Watermarking Technique for IP Core Protection on FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  17. Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris
    IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:578-591 [Journal]

  18. A Precise Electrical Disturbance Generator for Neural Network Training with Real Level Output. [Citation Graph (, )][DBLP]


  19. Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing. [Citation Graph (, )][DBLP]


  20. Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. [Citation Graph (, )][DBLP]


  21. Enhancing ADC resolution through Field Programmable Analog Array dynamic reconfiguration. [Citation Graph (, )][DBLP]


  22. A Proposal to Improve the Simple Query Interface (SQI) of Learning Objects Repositories. [Citation Graph (, )][DBLP]


  23. Tool for Generation IMS-QTI v2.1 Files with Java Server Faces. [Citation Graph (, )][DBLP]


  24. Wine Classification with Gas Sensors Combined with Independent Component Analysis and Neural Networks. [Citation Graph (, )][DBLP]


  25. A mobile learning tool to deliver online questionnaires. [Citation Graph (, )][DBLP]


  26. Development and Use of an Evaluation Collection for Personalisation of Digital Newspapers. [Citation Graph (, )][DBLP]


Search in 0.016secs, Finished in 0.017secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002