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Uwe Meyer-Bäse: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Antonio García, Javier Ramírez, Uwe Meyer-Bäse, Encarnación Castillo, Antonio Lloris-Ruíz
    Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:531-534 [Conf]
  2. Uwe Meyer-Bäse, Javier Ramírez, Antonio García
    Low Power High Speed Algebraic Integer Frequency Sampling Filters Using FPLDs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:897-904 [Conf]
  3. Uwe Meyer-Bäse
    Coherent Demodulation with FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:166-175 [Conf]
  4. Uwe Meyer-Bäse
    Convolutional Error Decoding with FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:376-380 [Conf]
  5. Uwe Meyer-Bäse, Anke Meyer-Bäse, W. Hilberg
    COordinate Rotation DIgital Computer (CORDIC) Synthesis for FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:397-408 [Conf]
  6. Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
    Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:384-393 [Conf]
  7. Javier Ramírez, Uwe Meyer-Bäse, Antonio García, Antonio Lloris-Ruíz
    Design and Implementation of RNS-Based Adaptive Filters. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1135-1138 [Conf]
  8. Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz, F. J. Taylor
    RNS implementation of FIR filters based on distributed arithmetic using field-programmable logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:486-489 [Conf]
  9. Javier Ramírez, Uwe Meyer-Bäse, Antonio García
    Efficient Rns-based Design of Programmable Fir Filters Targeting Fpl Technology. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:1, pp:165-177 [Journal]
  10. Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris, Uwe Meyer-Bäse
    IPP Watermarking Technique for IP Core Protection on FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  11. Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris
    IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:578-591 [Journal]
  12. Uwe Meyer-Bäse, Thanos Stouraitis
    New power-of-2 RNS scaling scheme for cell-based IC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:280-283 [Journal]

  13. Improved gradient-based motion estimation on reconfigurable platforms. [Citation Graph (, )][DBLP]


  14. Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. [Citation Graph (, )][DBLP]


  15. A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters. [Citation Graph (, )][DBLP]


  16. An interspike interval method for computing phase locking from neural firing. [Citation Graph (, )][DBLP]


  17. Artificial implementation of auditory neurons: A comparison of biologically motivated models and a new transfer function oriented model. [Citation Graph (, )][DBLP]


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