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Publications of Author

1. Ivan Gonzalez, Sergio López-Buedo, Francisco J. Gómez, Javier Martínez
   Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:194-203 [Conf]
   
2. Ivan Gonzalez, Javier Sanchez-Pastor, Jorge L. Hernandez-Ardieta, Francisco J. Gomez-Arribas, Javier Martínez
   Using Reconfigurable Hardware Through Web Services in Distributed Applications. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1110-1112 [Conf]
   
3. Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio López-Buedo
   Hardware-Accelerated SSH on Self-Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   FPT, 2005, pp:289-290 [Conf]
   
4. Javier Sanchez-Pastor, Ivan Gonzalez, Jorge López, Francisco J. Gomez-Arribas, Javier Martínez
   A Remote Laboratory for Debugging FPGA-Based Microprocessor Prototypes. [Citation Graph (0, 0)][DBLP]
   ICALT, 2004, pp:- [Conf]
   
5. Ruben Cabello, Ivan Gonzalez, Francisco J. Gómez, Javier Martínez
   A Web Laboratory for a Basic Electronics Course. [Citation Graph (0, 0)][DBLP]
   WebNet, 2001, pp:816-821 [Conf]
   
6. Arnaud Lagger, Andres Upegui, Eduardo Sanchez, Ivan Gonzalez
   Self-Reconfigurable Pervasive Platform for Cryptographic Application. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-4 [Conf]
   
7. J. Gonzalez-Gomez, Ivan Gonzalez, Francisco J. Gomez-Arribas, Eduardo I. Boemo
   Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. [Citation Graph (0, 0)][DBLP]
   ARC, 2006, pp:24-29 [Conf]
   
8. Ivan Gonzalez, Estanislao Aguayo, Sergio López-Buedo
   Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2007, v:27, n:4, pp:49-57 [Journal]
   
9. 
   A Framework to Improve IP Portability on Reconfigurable Computers. [Citation Graph (, )][DBLP]
   
   
10. 
    Bringing High-Performance Reconfigurable Computing to Exact Computations. [Citation Graph (, )][DBLP]
    
    
11. 
    Performance bounds of partial run-time reconfiguration in high-performance reconfigurable computing. [Citation Graph (, )][DBLP]