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Publications of Author

1. Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
   Fly - A Modifiable Hardware Compiler. [Citation Graph (0, 0)][DBLP]
   FPL, 2002, pp:381-390 [Conf]
   
2. Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
   IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:526-535 [Conf]
   
3. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
   Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:1111-1114 [Conf]
   
4. Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner
   Prototyping of a High Performance Generic Viterbi Decoder. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2002, pp:42-47 [Conf]
   
5. Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner
   Rapid Prototyping of an Integrated Testing and Debugging Unit. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2004, pp:187-192 [Conf]
   
6. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
   Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2002, pp:138-0 [Conf]
   
7. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesus, Ocampo Hidalgo, Manfred Glesner
   Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. [Citation Graph (0, 0)][DBLP]
   IEEE International Workshop on Rapid System Prototyping, 2003, pp:172-178 [Conf]
   
8. Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner
   A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. [Citation Graph (0, 0)][DBLP]
   VLSI-SOC, 2003, pp:44-49 [Conf]