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Publications of Author

1. Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker
   Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1037-1041 [Conf]
   
2. Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
   Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2007, pp:41-46 [Conf]
   
3. 
   Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. [Citation Graph (, )][DBLP]
   
   
4. 
   A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. [Citation Graph (, )][DBLP]
   
   
5. 
   Data path driven waveform-like reconfiguration. [Citation Graph (, )][DBLP]
   
   
6. 
   Fine grain reconfigurable architectures. [Citation Graph (, )][DBLP]
   
   
7. 
   Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. [Citation Graph (, )][DBLP]
   
   
8. 
   An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. [Citation Graph (, )][DBLP]
   
   
9. 
   FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. [Citation Graph (, )][DBLP]
   
   
10. 
    Data reallocation by exploiting FPGA configuration mechanisms. [Citation Graph (, )][DBLP]