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Publications of Author

1. Peter Jamieson, Jonathan Rose
   A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:305-310 [Conf]
   
2. Peter Jamieson, Angelos Bilas
   CableS: Thread Control and Memory Management Extensions for Shared Virtual Memory Clusters. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:263-274 [Conf]
   
3. Peter Jamieson, Angelos Bilas
   CableS : Thread Control and Memory System Extensions for Shared Virtual Memory Clusters. [Citation Graph (0, 0)][DBLP]
   WOMPAT, 2001, pp:170-184 [Conf]
   
4. Angelos Bilas, Courtney R. Gibson, Reza Azimi, Rosalia Christodoulopoulou, Peter Jamieson
   Using System Emulation to Model Next-Generation Shared Virtual Memory Clusters. [Citation Graph (0, 0)][DBLP]
   Cluster Computing, 2003, v:6, n:4, pp:325-338 [Journal]
   
5. 
   Harnessing Human Computation Cycles for the FPGA Placement Problem. [Citation Graph (, )][DBLP]
   
   
6. 
   Benchmarking Reconfigurable Architectures in the Mobile Domain. [Citation Graph (, )][DBLP]
   
   
7. 
   VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. [Citation Graph (, )][DBLP]
   
   
8. 
   Towards benchmarking energy efficiency of reconfigurable architectures. [Citation Graph (, )][DBLP]
   
   
9. 
   Adopting a studio-based education approach into information technology (poster session). [Citation Graph (, )][DBLP]