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Jörg Brakensiek: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
    Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1111-1114 [Conf]
  2. Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner
    Dynamic power optimization of the trace-back process for the Viterbi algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:721-724 [Conf]
  3. Holger Blume, Daniel Becker, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
    Hybrid Functional and Instruction Level Power Modeling for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:216-226 [Conf]
  4. Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner
    An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:167-0 [Conf]
  5. Holger Blume, Jörg von Livonius, Lisa Rotenberg, Tobias G. Noll, Harald Bothe, Jörg Brakensiek
    Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform. [Citation Graph (0, 0)][DBLP]
    ICSAMOS, 2007, pp:74-81 [Conf]
  6. Holger Blume, Daniel Becker, Lisa Rotenberg, Martin Botteck, Jörg Brakensiek, Tobias G. Noll
    Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:10, pp:689-702 [Journal]

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