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Publications of Author

1. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   An Efficient Technique for Mapping RTL Structures onto FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 1994, pp:99-110 [Conf]
   
2. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. [Citation Graph (0, 0)][DBLP]
   FPL, 1995, pp:139-148 [Conf]
   
3. C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer
   High Level Design Experiences with IDEAS. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1993, pp:110- [Conf]
   
4. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   FAST: FPGA Targeted RTL Structure Synthesis Technique. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:21-24 [Conf]
   
5. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   Optimal Clock Period for Synthesized Data Paths. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1997, pp:134-139 [Conf]
   
6. A. R. Naseer, M. Balakrishnan, Anshul Kumar
   Direct mapping of RTL structures onto LUT-based FPGA's. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:7, pp:624-631 [Journal]
   
7. Ismat K. Maarouf, A. R. Naseer
   WSNodeRater - An Optimized Reputation System Framework for Security Aware Energy Efficient Geographic Routing in WSNs. [Citation Graph (0, 0)][DBLP]
   AICCSA, 2007, pp:258-265 [Conf]
   
8. 
   SNARE: sensor node attached reputation evaluator. [Citation Graph (, )][DBLP]