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Luis Parrilla: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Luis Parrilla, Encarnación Castillo, Antonio García, Antonio Lloris-Ruíz
    Intellectual Property Protection for RNS Circuits on FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:1139-1141 [Conf]
  2. Javier Ramírez, Antonio García, Pedro G. Fernández, Luis Parrilla, Antonio Lloris-Ruíz
    Analysis of RNS-FPL Synergy for High Throughput DSP Applications: Discrete Wavelet Transform. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:342-351 [Conf]
  3. Julio Ortega, Luis Parrilla, José Luis Bernier, Consolación Gil, Begoña Pino, Mancia Anguita
    Adaptive Cooperation Between Processors in a Parallel Boltzmann Machine. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 1999, pp:208-218 [Conf]
  4. Julio Ortega, Luis Parrilla, Alberto Prieto, Antonio Lloris-Ruíz, Carlos García Puntonet
    Modified Boltzmann Machine for an Efficient Distributed Implementation. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:1221-1232 [Conf]
  5. Daniel González, Luis Parrilla, Antonio García, Encarnación Castillo, Antonio Lloris-Ruíz
    Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:657-665 [Conf]
  6. Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris-Ruíz
    A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:188-197 [Conf]
  7. Luis Parrilla, Julio Ortega, Antonio Lloris-Ruíz
    Using PVM for Distributed Logic Minimization in a Network of Computers. [Citation Graph (0, 0)][DBLP]
    PVM/MPI, 1999, pp:541-548 [Conf]
  8. Encarnación Castillo, Luis Parrilla, Antonio García, Antonio Lloris, Uwe Meyer-Bäse
    IPP Watermarking Technique for IP Core Protection on FPL Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  9. Encarnación Castillo, Uwe Meyer-Bäse, Antonio García, Luis Parrilla, Antonio Lloris
    IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:5, pp:578-591 [Journal]

  10. Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting. [Citation Graph (, )][DBLP]

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