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Fernando Moraes: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne
    Influence of Locig Block Layout Architecture on FPGA Performance. [Citation Graph (0, 0)][DBLP]
    FPL, 1994, pp:34-44 [Conf]
  2. Fernando Moraes, Michel Robert, Daniel Auvergne
    A Virtual CMOS Library Approach for East Layout Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:415-426 [Conf]
  3. Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi
    Exploiting reconfigurability for low-power control of embedded processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:421-424 [Conf]
  4. Erico Bastos, Everton Carara, Daniel Pigatto, Ney Laert Vilar Calazans, Fernando Moraes
    MOTIM - A Scalable Architecture for Ethernet Switches. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:451-452 [Conf]
  5. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    A new hardware countermeasure for masking power signatures of crypto cores. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2005, pp:169-176 [Conf]
  6. Aline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes
    Virtual channels in networks on chip: implementation and evaluation on hermes NoC. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:178-183 [Conf]
  7. Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes
    Current mask generation: a transistor level security against DPA attacks. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:115-120 [Conf]
  8. Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes
    Infrastructure for dynamic reconfigurable systems: choices and trade-offs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2006, pp:44-49 [Conf]
  9. Leonel Tedesco, Aline Mello, Diego Garibotti, Ney Calazans, Fernando Moraes
    Traffic generation and performance evaluation for mesh-based NoCs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:184-189 [Conf]
  10. Ewerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes
    PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:10-15 [Conf]
  11. Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara
    From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:355-0 [Conf]
  12. Sandro Ferreira, Felipe Haffner, Luis Fernando Pereira, Fernando Moraes
    Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:105-110 [Conf]
  13. Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes
    DfT for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:435-440 [Conf]
  14. Leandro Möller, Ismael Grehs, Ney Calazans, Fernando Moraes
    Reconfigurable Systems Enabled by a Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  15. Daniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Moraes
    A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-8 [Conf]
  16. Leandro Möller, Ismael Grehs, Ewerson Carvalho, Rafael Soares, Ney Calazans, Fernando Moraes
    A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:23-30 [Conf]
  17. Everton Carara, Aline Mello, Fernando Moraes
    Communication Models in Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:57-60 [Conf]
  18. Luis Carlos Caruso, Guilherme Guindani, Hugo Schmitt, Ney Calazans, Fernando Moraes
    SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:27-33 [Conf]
  19. Ewerson Carvalho, Ney Calazans, Fernando Moraes
    Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:34-40 [Conf]
  20. Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes
    Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:213-218 [Conf]
  21. Aline Mello, Leandro Möller, Ney Calazans, Fernando Moraes
    MultiNoC: A Multiprocessing System Enabled by a Network on Chip [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  22. A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures. [Citation Graph (, )][DBLP]


  23. SCAFFI: An intrachip FPGA asynchronous interface based on hard macros. [Citation Graph (, )][DBLP]


  24. Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. [Citation Graph (, )][DBLP]


  25. Buffer sizing for QoS flows in wormhole packet switching NoCs. [Citation Graph (, )][DBLP]


  26. Router architecture for high-performance NoCs. [Citation Graph (, )][DBLP]


  27. A high abstraction, high accuracy power estimation model for networks-on-chip. [Citation Graph (, )][DBLP]


  28. A path-load based adaptive routing algorithm for networks-on-chip. [Citation Graph (, )][DBLP]


  29. Increasing NoC power estimation accuracy through a rate-based model. [Citation Graph (, )][DBLP]


  30. Validation of executable application models mapped onto network-on-chip platforms. [Citation Graph (, )][DBLP]


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