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Rawat Siripokarpirom :
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Rawat Siripokarpirom Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. [Citation Graph (0, 0)][DBLP ] FPL, 2004, pp:700-709 [Conf ] Rawat Siripokarpirom A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test. [Citation Graph (0, 0)][DBLP ] FPL, 2005, pp:505-508 [Conf ] Rawat Siripokarpirom Platform Development for Run-Time Reconfigurable Co-Emulation. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2006, pp:179-185 [Conf ] Rawat Siripokarpirom , Friedrich Mayer-Lindenberg Hardware-Assisted Simulation and Evaluation of IP Cores Using FPGA-Based Rapid Prototyping Boards. [Citation Graph (0, 0)][DBLP ] IEEE International Workshop on Rapid System Prototyping, 2004, pp:96-102 [Conf ] Search in 0.001secs, Finished in 0.001secs