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Publications of Author

1. Sinan Yalcin, Hasan F. Ates, Ilker Hamzaoglu
   A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:509-514 [Conf]
   
2. Ilker Hamzaoglu, Janak H. Patel
   Reducing Test Application Time for Full Scan Embedded Cores. [Citation Graph (0, 0)][DBLP]
   FTCS, 1999, pp:260-267 [Conf]
   
3. Ilker Hamzaoglu, Janak H. Patel
   Deterministic Test Pattern Generation Techniques for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2000, pp:538-543 [Conf]
   
4. Ilker Hamzaoglu, Janak H. Patel
   Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1998, pp:283-289 [Conf]
   
5. Ilker Hamzaoglu, Janak H. Patel
   Compact two-pattern test set generation for combinational and full scan circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1998, pp:944-953 [Conf]
   
6. Hillol Kargupta, Ilker Hamzaoglu, Brian Stafford
   Scalable, Distributed Data Mining - An Agent Architecture. [Citation Graph (0, 0)][DBLP]
   KDD, 1997, pp:211-214 [Conf]
   
7. Ilker Hamzaoglu, Janak H. Patel
   Reducing Test Application Time for Built-in-Self-Test Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
   VTS, 2000, pp:369-376 [Conf]
   
8. Ilker Hamzaoglu, Janak H. Patel
   New Techniques for Deterministic Test Pattern Generation. [Citation Graph (0, 0)][DBLP]
   VTS, 1998, pp:446-452 [Conf]
   
9. Mustafa Parlak, Ilker Hamzaoglu
   An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter. [Citation Graph (0, 0)][DBLP]
   AHS, 2006, pp:381-385 [Conf]
   
10. Ilker Hamzaoglu, Janak H. Patel
    Test set compaction algorithms for combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:957-963 [Journal]
    
11. Esra Sahin, Ilker Hamzaoglu
    Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:183-188 [Conf]
    
12. Sinan Yalcin, Ilker Hamzaoglu
    A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:63-67 [Conf]
    
13. 
    A high performance reconfigurable Motion Estimation hardware architecture. [Citation Graph (, )][DBLP]
    
    
14. 
    A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation. [Citation Graph (, )][DBLP]
    
    
15. 
    An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. [Citation Graph (, )][DBLP]
    
    
16. 
    An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. [Citation Graph (, )][DBLP]
    
    
17. 
    A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation. [Citation Graph (, )][DBLP]
    
    
18. 
    A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video. [Citation Graph (, )][DBLP]
    
    
19. 
    Low power techniques for Motion Estimation hardware. [Citation Graph (, )][DBLP]
    
    
20. 
    An efficient H.264 intra frame coder system design. [Citation Graph (, )][DBLP]
    
    
21. 
    A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. [Citation Graph (, )][DBLP]