The SCEAS System
Navigation Menu

Search the dblp DataBase


Hungse Cha: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hungse Cha, Elizabeth M. Rudnick, Gwan S. Choi, Janak H. Patel, Ravishankar K. Iyer
    A Fast and Accurate Gate-Level Transient Fault Simulation Environment. [Citation Graph (0, 0)][DBLP]
    FTCS, 1993, pp:310-319 [Conf]
  2. Abhijit Dharchoudhury, Sung-Mo Kang, H. Cha, J. H. Patel
    Fast timing simulation of transient faults in digital circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:719-722 [Conf]
  3. Hungse Cha, Janak H. Patel
    A Logic-Level Model for alpha-Paricle Hits in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:538-542 [Conf]
  4. Hungse Cha, Janak H. Patel
    Latch Design for Transient Pulse Tolerance. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:385-388 [Conf]
  5. Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi
    A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:11, pp:1248-1256 [Journal]

Search in 0.001secs, Finished in 0.002secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002