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Trung A. Diep: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Trung A. Diep, John Paul Shen
    Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:100-109 [Conf]
  2. Murali Annavaram, Trung A. Diep, John Paul Shen
    Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:242-248 [Conf]
  3. Trung A. Diep, Mikko H. Lipasti, John Paul Shen
    Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:86-93 [Conf]
  4. Trung A. Diep, Christopher Nelson, John Paul Shen
    Performance Evaluation of the PowerPC 620 Microarchitecture. [Citation Graph (0, 0)][DBLP]
    ISCA, 1995, pp:163-175 [Conf]
  5. Trung A. Diep, John Paul Shen, Mike Phillip
    EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:225-235 [Conf]
  6. Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
    Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:151-164 [Conf]
  7. Trung A. Diep, John Paul Shen
    VMW: A Visualization-Based Microarchitecture Workbench. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1995, v:28, n:12, pp:57-64 [Journal]
  8. Partha Kundu, Murali Annavaram, Trung A. Diep, John Shen
    A case for shared instruction cache on chip multiprocessors running OLTP. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:11-18 [Journal]

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